Intel® Open Source HD Graphics and Intel Iris™ Plus Graphics
Programmer's Reference Manual
For the 2016 - 2017 Intel Core™ Processors, Celeron™ Processors,
and Pentium™ Processors based on the "Kaby Lake" Platform
Volume 10: HEVC Codec Pipeline (HCP)
January 2017, Revision 1.0
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Doc Ref # IHD-OS-KBL-Vol 10-1.17
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HEVC
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Table of Contents
High Efficiency Video Coding (HEVC) Introduction .................................................................. 1
Scope ............................................................................................................................................................................ 1
Summary of Features ..................................................................................................................... 1
HCP Hardware Pipeline Features ....................................................................................................................... 1
HEVC Decoder Features......................................................................................................................................... 2
HEVC Encoder Features ......................................................................................................................................... 2
Architecture Overview ................................................................................................................... 5
VP9 Decoder .............................................................................................................................................................. 5
HCP Command Summary .............................................................................................................. 5
Workload Command Model ................................................................................................................................ 5
HCP Command Sequence Examples............................................... Error! Bookmark not defined.
HCP Decoder Command Sequence ......................................................................................................... 7
HCP Encoder Command Sequence ......................................................................................................... 8
Memory Address Attributes ............................................................................................................................... 10
HCP Pipe Common Commands ....................................................................................................................... 10
Buffer Size Requirements .................................................................................................................................... 11
VP9 Common Commands .................................................................................................................................. 13
HCP Common Commands.................................................................................................................................. 13
VP9 Commands ...................................................................................................................................................... 14
Tile Size and CU Stream-out Records ....................................................................................................... 14
Stream-in Probability Table ............................................................................................................................. 1
Stream-in formats for creating compressed header ............................................................................. 1
Probability Statistics Counters Table ........................................................................................................... 2
VP9 PAK Quant Lookup Tables ...................................................................................................................... 1
SB, CU/PU and TU Sizes Encoder Only .................................................................................................. 15
Definition of the VP9 CU Record Structure - Encoder Only ............................................................. 16
Allowed SB Size Encoder Only ..................................................................................................................... 21
HCP Commands ...................................................................................................................................................... 21
Multipass flow during BRC and SAO ......................................................................................................... 22
CU and Slice level stat streamOut............................................................................................................... 23
Definition of the CU Record Structure for Ext Interface Encoder Only..................................... 24
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LCU, CU, TU, and PU Sizes Encoder Only ............................................................................................. 28
Allowed LCU Size Encoder Only ............................................................................................................... 32
HEVC Error Concealment ............................................................................................................. 33
VP9 Register Definitions .............................................................................................................. 35
Register Attributes Description ........................................................................................................................ 35
VP9 Register Map ................................................................................................................................................... 35
VP9 Encoder Register Descriptions ................................................................................................................. 35
HEVC Register Definitions ........................................................................................................... 35
Register Attributes Description ........................................................................................................................ 36
HCP Decoder Register Map ............................................................................................................................... 36
HCP Decoder Register Descriptions ............................................................................................................... 36
HCP Encoder Register Map ................................................................................................................................ 36
HCP Encoder Register Descriptions ................................................................................................................ 36
HUC Status Register Descriptions ................................................................................................................... 37
Acronyms and Applicable Standards ......................................................................................... 37
Acronyms and Abbreviations ............................................................................................................................ 37
HEVC
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1
High Efficiency Video Coding (HEVC) Introduction
The HEVC Codec Pipeline (HCP) is a fixed function hardware video codec responsible for decoding and
encoding HEVC (High Efficiency Video Coding) video streams.
Scope
The primary scope of the HCP BSpec document is to provide a description of the HCP commands
processed by the Video Command Streamer (VCS). The secondary scope is to provide a description of
the status registers on the Message Channel Interface to support encoding and decoding of the HEVC
video format.
The BSpec sections include:
Summary of Features
Architecture Overview
Commands
Register Definitions
Acronyms and Applicable Standards
Summary of Features
The following sections define the HEVC Decoder and Encoder general features and the features specific
to HEVC decoding and encoding, respectively.
HCP Hardware Pipeline Features
Supports both decoder and encoder functions, setup on a per picture basis:
Hardware acceleration provides Ctb/CU level decode and encode.
No context switch is supported within a frame process.
Supports Video Command Streamer (VCS):
Shared with MFX HW pipeline, and at any one time, only one pipeline (MFX or HCP) and one
operation (decoding or encoding) can be active.
Supports Message Channel Interface:
Feature
Supports Tile-YS and Tile-YF.
Supports Tile-Y Legacy.
Supports NV12 video buffer plane:
Supports 4:2:0, 8-bit per pixel component (Y, Cb and Cr) video.
Supports 8Kx8K frame size.
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HEVC Decoder Features
Supports full-featured HEVC Main Profile standard, up to Level 6.2.
Supports the long format HW decoding interface:
All headers (SPS, PPS, Slice Header) are parsed and decoded outside the HCP HW pipeline.
They are then fed to the HW through a set of HCP state commands.
Supports inner-loop decode with hardware entry points for Encoder.
Error detection/resiliency down to the Ctb/CU level.
HEVC Encoder Features
Supports ENC-PAK architecture
Supports multiple pass BRC rate control operation flow
Supports the HEVC Main Profile standard, with certain restrictions on the feature set and coding
parameters, listed in the following table:
HEVC Encoder Features and Restrictions
Note that there is a difference between what PAK supported and what ENC supported. A
feature/function that is supported in the PAK, does not necessary being supported by ENC and
MediaSDK and the like.
Coding Tool
Gen9
Support
Gen9
Restriction
Comments
LCU Size
Yes
(spec)
Support all 3 sizes: 16x16, 32x32, 64x64.
CU Size
Yes
(spec)
Support 8x8, 16x16, 32x32, 64x64.
Max 64 CU per LCU; min. CU size intel supported is 8x8 for all LCU size.
PU Partition
Yes
(spec)
Support all inter symmetric (square) and asymmetric (non-square) PU
partitioning, according to HEVC spec. PU Size for inter : Smallest allowed
is 4x8 and 8x4, and they cannot be bidirectional. Inter 4x4 PU is not
allowed in Main Profile.
TU QuadTree
Partial (intel)
max depth is
set to 3
Max depth is 3 (64x64 CU with 4x4 TU). Decoder supports this depth,
but probably no need to search this for encode. Better to just split CU.
HM common conditions set the max to 2 for both inter and intra.
Intel Encoder only supports 2 levels of quad-tree. That is,
max_transform_hierarchy_depth_inter/intra <= 2.
Max num of TUs per CU is 16.
AMP
Yes
(spec)
Asymmetric Motion Partition (rectangular PU partitioning - 2NxnU,
2NxnD, nLx2N or nRx2N). Available only for 64x64 to 16x16 CU.
AMVP
Yes
(spec)
Adaptive/Advanced Motion Vector Prediction : spatial and PU-based
temporal co-located MV candidates with scaling. Logic available from
decoder. HW PAK is supporting temporal MV candidates.
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Coding Tool
Gen9
Support
Gen9
Restriction
Comments
Merge
Yes
(spec)
Merge Skip and Regular Merge. Max. 5 MV Merge candidates (4 spatial
+ 1 temporal co-located) with scaling. Logic available from decoder.
[merge_flag, merge_index, skip_flag]
Parallel Motion
Merge
No (intel)
Tool for parallel decode of MVs. Since this isn’t constrained by Main
Profile, the decoder has to meet performance targets in the worst case
anyway.
MC
Interpolation
Filter
Yes
(spec)
¼-pel Luma MV precision, 1/8-pel Chroma MV precision. 8-tap Luma
filtering for both ½-pel and ¼-pel locations (1-pass). 4-tap Chroma
filtering. Use separable (first horizontal then vertical 1-D filtering) filter
coefficients. Not all filter kernels are symmetrical and can map into
simple arithmetic. It is a DCT-IF based filter. All operations are within 16-
bit data.
Weighted
Prediction
Yes
(spec)
Free for PAK since decoder already has it. Cross fade and fade-in/out
detection required by VME. VME must supply weights, implicit weighted
prediction is not supported in HEVC. Only explicit weight is supported.
They are both unidirectional and bidirectional.
Combined
Reference
Frame List
No (intel)
Combine List0 and List1 into a single list to remove uni-prediction
signaling overhead.
Intra modes
Yes
(spec)
33 directions and DC/Planar modes, with adaptive pre-filtering on
reference pixels and boundary smoothing.
Intel ENC-VME Mode search reduction for large CUs (64x64 and 32x32)
for performance speed up with minimal loss.
IPCM (intra)
No (intel)
Can be disabled completely by SPS, or only allowed at certain CU sizes.
No bit maximum on CUs in any profile/level (yet), so as of today there’s
no mandate to support this for encode.
Gen9 PAK does not support IPCM, so ENC cannot generate IPCM mode.
Constrained
Intra
No (intel)
Allow only intra neighboring blocks for current block intra-prediction.
Enabling this is a coding loss and does not result in a performance
improvement in HW designs.
2D DCT
Transform
Yes
(spec)
Square shape only; 32x32, 16x16, 8x8 and 4x4.
Transform Skip
Evaluation
No (intel)
ENC will
estimate the
use of
transform skip
Significant coding gains for screen content (PowerPoint etc.). This tool is
disabled in the common conditions but isn’t explicitly disallowed by
Main Profile. FQ is not bypass.
Sign bit hiding
No (intel)
Coding gain by removing one bypass bin per TU. Requires some smarts
in the PAK.
Trellis
No (intel)
Trellis Quantization
SAO
No (intel)
Difficult to implement in single pass, performance impact in 2-pass or
with previous frame search. Needs investigation. Decoder will support it.
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Coding Tool
Gen9
Support
Gen9
Restriction
Comments
Loop Filter
across
tiles/slices
boundary
No (intel)
Can be disabled for tiles and or slices in SPS, so that filter across all tiles
and slices boundaries. Main profile doesn’t constrain.
Scaling List
Yes
(spec)
This uses the default (or custom) qp adjustment on a per-frequency
basis within a TU. Good coding improvement over flat scaling.
dQP
Partial (intel)
Yes for LCU;
No for CU
Being able to change QP per LCU or even up to once per 8x8 CU can
lead to significant coding gains. Not sure how easy it is for VME to
decide qp values though.
Chroma QP
offset
No (intel)
No ROI.
Dependent
slices
No (intel)
It is now part of Main Profile, but Intel will not support it. SW can
perform the slice repackaging without re-encoding.
Tiles
No (intel)
Although in Main Profile, it results in coding loss and doesn’t improve
performance on HW. SW parallel processing (multithreaded) tool
Wavefront (aka
WPP)
No (intel)
Latest Main Profile spec has included Wavefront. We got a feedback
that this feature is highly desirable to support high performance
multithreading HEVC decoder.
Lossless
coding
No (intel)
Note: this is not the same as IPCM. Also details of this are in flux.
Interlaced
Video
No (intel)
Only progressive video encoding is supported.
LM mode
No
(spec)
Chroma-from-luma intra prediction (Linear Mode) is not allowed in
Main Profile (yet).
NSQT
No
(spec)
Non square transform is not allowed in the Main Profile
ALF
No
(spec)
Expensive and not in Main Profile currently. If decoder is going to
support it, may consider for encoder as well.
Entropy slices
No
(spec)
Not allowed in Main Profile, it is a SW parallel processing
(multithreaded) tool.
Slice
granularity !=
0
No
(spec)
Not allowed by Main Profile, and highly likely to be removed from the
standard completely.
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Architecture Overview
This section discusses HEVC features as follows:
Name
VP9 Decoder
VP9 Decoder
The HCP Decoder, following diagram, is a hardware based pipeline that accelerates the stream decode
for an external Host Processor. The Host Processor is defined as a system processor external to the HCP
that is responsible for high level parsing of the elementary stream and workload creation.
HCP Command Summary
The HCP is configured for encoding or decoding through a set of batch commands defined in the
following sections. The software driver builds a frame level workload using these commands and stores
these workloads in graphics memory where they are fetched by the Video Command Streamer (VCS) and
presented to the HCP for processing. The commands are processed by the Workload Parser within the
HCP and the hardware is configured by the Workload Parser prior to each frame level encode or decode.
A workload is defined as a set of commands necessary to encode or decode one frame.
The software driver is required to read the HCP disable fuse to determine if the HCP is enabled. If it is
disabled, then the software driver must not enable HCP batch commands to be sent to the HCP or a
hang event may occur. Only when the HCP is enabled through the fuse, should the batch commands be
sent to the HCP.
Workload Command Model
DWord0 of each command is defined in HCP DWord0 Command Definition. The HCP is selected with the
Media Instruction Opcode “7h” for all HCP Commands.
HCP DWord0 Command Definition
DWord
Bits
Description
0
31:29
Command Type = PARALLEL_VIDEO_PIPE = 3h
28:27
Pipeline Type = 2h
26:23
Media Instruction Opcode = Codec/Engine Name = HCP = 7h
22:16
Media Instruction Command = <see Workload Command Model >
15:12
Reserved: MBZ
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DWord
Bits
Description
11:0
Dword Length (Excludes Dwords 0, 1) = <command length>
Each HCP command has assigned a media instruction command as defined in HCP Media Instruction
Commands (Opcode=7h).
HCP Media Instruction Commands (Opcode=7h)
Media Instruction Command
Command DWord0 [22:16]
Gen9 Mode
Scope
HCP_PIPE_MODE_SELECT
0h
Enc/Dec
Picture
HCP_SURFACE_STATE
1h
Enc/Dec
Picture
HCP_PIPE_BUF_ADDR_STATE
2h
Enc/Dec
Picture
HCP_IND_OBJ_BASE_ADDR_STATE
3h
Enc/Dec
Picture
HCP_QM_STATE
4h
Enc/Dec
Picture
HCP_FQM_STATE (encoder only)
5h
Enc
Picture
Reserved
8h-Fh
HCP_PIC_STATE
10h
Enc/Dec
Picture
HCP_TILE_STATE
11h
Dec
Picture
HCP_REF_IDX_STATE
12h
Enc/Dec
Slice
HCP_WEIGHTOFFSET
13h
Enc/Dec
Slice
HCP_SLICE_STATE
14h
Enc/Dec
Slice
Reserved
15h-1Fh
HCP_BSD_OBJECT_STATE (decoder only)
20h
Dec
Slice
HCP_PAK_OBJECT (encoder only)
21h
Enc
LCU
HCP_INSERT_PAK_OBJECT (encoder only)
22h
Enc
Bitstream
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7
HCP Decoder Command Sequence
The long format workload for the HCP is based upon a single frame decode. There are no states saved
between frame decodes in the HCP. Once the bit stream DMA is configured with the HCP_BSD_OBJECT
command, and the bit stream is presented to the HCP, the frame decode will begin.
HCP Long Format Decode Workload Flowchart
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HCP Encoder Command Sequence
For a single frame encoding process (w/o multiple slices per frame), the command sequence is listed
below. There are no states saved between frame encoded in the HCP. There should be no other
commands or context switch within a group of PAK OBJECT Commands, representing a complete slice.
HCP and MFX share the same VCS, but there is no common encoding and decoding command that can
be executed in both pipes mi_flush and MMIO commands.
------ Per Frame Level Commands
HCP_PIPE_MODE_SELECT
HCP_SURFACE_STATE
HCP_PIPE_BUF_ADDR_STATE
HCP_IND_OBJ_BASE_ADDR_STATE
HCP_FQM_STATE issue n number of times
HCP_QM_STATE issue n number of times
HCP_PIC_STATE
------- Per Slice Level Commands (2 cases)
------- A Frame with only 1 Slice:
HCP_REF_IDX_STATE set to provide L0 list for a P or B-Slice
HCP_REF_IDX_STATE set to provide L1 list for a B-Slice
HCP_WEIGHTOFFSET_STATE Command set to provide for L0 of a P or B-Slice
HCP_WEIGHTOFFSET_STATE Command - set to provide for L1 of a B-Slice
HCP_SLICE_STATE
HCP_PAK_INSERT_OBJECT if header present at 1st slice start
------- A group of LCUs Per Slice
HCP_PAK_OBJECT
HCP_PAK_INSERT_OBJECT if tail present at frame end
MI_FLUSH when the frame is done
------ A Frame with Multiple Slices:
HCP_REF_IDX_STATE set to provide L0 list for a P or B-Slice
HCP_REF_IDX_STATE set to provide L1 list for a B-Slice
HCP_WEIGHTOFFSET_STATE Command set to provide for L0 of a P or B-Slice
HCP_WEIGHTOFFSET_STATE Command - set to provide for L1 of a B-Slice
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HCP_SLICE_STATE
HCP_PAK_INSERT_OBJECT if header present at 1st slice start of a frame
HCP_PAK_OBJECT - a group of LCUs for a slice or a frame
HCP_PAK_INSERT_OBJECT if tail present at slice or frame end
HCP_REF_IDX_STATE set to provide L0 list for a P or B-Slice
HCP_REF_IDX_STATE set to provide L1 list for a B-Slice
HCP_WEIGHTOFFSET_STATE Command set to provide for L0 of a P or B-Slice
HCP_WEIGHTOFFSET_STATE Command - set to provide for L1 of a B-Slice
HCP_SLICE_STATE
HCP_PAK_INSERT_OBJECT if header present at slice start
HCP_PAK_OBJECT - a group of LCUs for a slice or a frame
HCP_PAK_INSERT_OBJECT if tail present at last slice end (frame end)
MI_FLUSH when the frame is done
---------
MFX_STITCH_OBJECT a generic bitstream stitching command from MFX pipe
MI_FLUSH
MI_FLUSH is not allowed between Slices. HEVC CABAC has simplified its operation from AVC. There is
no longer a BSP_BUF_BASE_ADDR_STATE Command, as only a small local internal buffer is needed for
BSP/BSE row store. THE HCP PAK_INSERT_OBJECT has been designed to support both inline and
indirectly payload. Nevertheless, the MFX_STITCH_OBJECT command can still be used to stitch HEVC
bitstreams together, and is run in the MFX pipe. No HEVC specific STITCH command is implemented. The
SURFACE_STATE command for HEVC is redesigned and much simplified from that of MFX pipe.
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Memory Address Attributes
This section defines the memory address attributes for the third DWord of the HCP command buffer
address.
NOTE: The first DWord defines the lower address range and the second Dword defines the upper address
range in the HCP command buffer address.
MemoryAddressAttributes
HCP Pipe Common Commands
The HCP Pipe Common Commands specify the HEVC Decoder pipeline level configuration.
Commands
HCP_PIPE_MODE_SELECT (VideoCS)
HCP_SURFACE_STATE (VideoCS)
HCP_PIPE_BUF_ADDR_STATE (VideoCS)
Buffer Name
Minimum Size in CLs
Notes
Deblocking Filter Line Buffer
((picture_width_in_pixels + 31) & (-32)) » 3
Eq. ensures
multiple of 4
Deblocking Filter Tile Line
Buffer
((picture_width_in_pixels + 31) & (-32)) » 3
Eq. ensures
multiple of 4
Deblocking Filter Tile
Column Buffer
((picture_height_in_pixels + 6*pic_height_in_ctb + 31) & (-32)) » 3
Eq. ensures
multiple of 4
Metadata Line Buffer (all
intra slices)
(picture_width_in_pixels + pic_width_in_lcu*8 + 1023) » 9
Eq. ensures
multiple of 2
Metadata Tile Line Buffer (all
intra slices)
(picture_width_in_pixels + pic_width_in_lcu *16 + 1023) » 9
Eq. ensures
multiple of 2
Metadata Tile Column Buffer
(all intra slices)
(picture_height_in_pixels + picture_height_in_pixels *8 + 1023) » 9
Eq. ensures
multiple of 2
Metadata Line Buffer (some
inter slices)
(((picture_width_in_pixels+15)»4)*188 + pic_width_in_lcu*9 + 1023) »
9
Eq. ensures
multiple of 2
Metadata Tile Line Buffer
(some inter slices)
(((picture_width_in_pixels +15)»4)*172 + pic_width_in_lcu *9 + 1023) »
9
Eq. ensures
multiple of 2
Metadata Tile Column Buffer
(some inter slices)
(((picture_height_in_pixels +15)»4)*176 + picture_height_in_lcu *89 +
1023) » 9
Eq. ensures
multiple of 2
SAO Line Buffer
(((picture_width_in_pixels » 1) + pic_width_in_ctb * 3)+15) & (-16)) » 3
Eq. ensures
multiple of 2
SAO Tile Line Buffer
(((picture_width_in_pixels » 1) + picture_width_in_ctb * 6)+15) & (-16))
» 3
Eq. ensures
multiple of 2
SAO Tile Column Buffer
(((picture_height_in_pixels » 1) + pic_height_in_ctb * 6)+15) & (-16)) »
3
Eq. ensures
multiple of 2
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Buffer Name
Minimum Size in CLs
Notes
Current and Collocated
Motion Vector Temporal
Buffer (lcu=16x16)
(((picture_width_in_pixels+63)»6)*((picture_height_in_pixels+15)»4)
Eq. ensures
multiple of 2
Current and Collocated
Motion Vector Temporal
Buffer (lcu>16x16)
(((picture_width_in_pixels+31)»5)*((picture_height_in_pixels+31)»5)
Eq. ensures
multiple of 2
Internal Media Rowstore Table
If the internal Media Rowstore exists, driver should use the storage as the following table indicates.
HEVC Pipeline
Frame Width
DAT
DF
SAO
DAT Addr
DF Addr
SAO Addr
HEVC
<= 2048
Y
Y
Y
0
64
320
2048 < x <= 4096
Y
Y
N
0
128
N/A
4096 < x <=8196
Y
N
N
0
N/A
N/A
Commands
HCP_IND_OBJ_BASE_ADDR_STATE (VideoCS)
HCP_QM_STATE (VideoCS)
HCP_FQM_STATE VideoCS
Buffer Size Requirements
HEVC Buffer Size Requirements (8 bit)
Buffer Name
Minimum Size in CLs
Notes
Deblocking Filter Line Buffer
((picture_width_in_pixels + 31) & (-32)) » 3
Eq. ensures
multiple of 4
Deblocking Filter Tile Line
Buffer
((picture_width_in_pixels + 31) & (-32)) » 3
Eq. ensures
multiple of 4
Deblocking Filter Tile
Column Buffer
((picture_height_in_pixels + 6*pic_height_in_ctb + 31) & (-32)) » 3
Eq. ensures
multiple of 4
Metadata Line Buffer (all
intra slices)
(picture_width_in_pixels + pic_width_in_lcu*8 + 1023) » 9
Eq. ensures
multiple of 2
Metadata Tile Line Buffer (all
intra slices)
(picture_width_in_pixels + pic_width_in_lcu *8 + 1023) » 9
Eq. ensures
multiple of 2
Metadata Tile Column Buffer
(all intra slices)
(picture_height_in_pixels + picture_height_in_lcu * 16 + 1023) » 9
Eq. ensures
multiple of 2
Metadata Line Buffer (some
inter slices)
(((picture_width_in_pixels+15)»4)*188 + pic_width_in_lcu * 9 + 1023) »
9
Eq. ensures
multiple of 2
Metadata Tile Line Buffer
(some inter slices)
(((picture_width_in_pixels +15)»4)*172 + pic_width_in_lcu * 9 + 1023) »
9
Eq. ensures
multiple of 2
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Buffer Name
Minimum Size in CLs
Notes
Metadata Tile Column Buffer
(some inter slices)
Equation:
(((picture_height_in_pixels +15)»4)*176 + picture_height_in_lcu * 89
+ 1023) » 9
Eq. ensures
multiple of 2
SAO Line Buffer
(((picture_width_in_pixels » 1) + pic_width_in_ctb * 3)+15) & (-16)) » 3
Eq. ensures
multiple of 2
SAO Tile Line Buffer
(((picture_width_in_pixels » 1) + picture_width_in_ctb * 6)+15) & (-16))
» 3
Eq. ensures
multiple of 2
SAO Tile Column Buffer
(((picture_height_in_pixels » 1) + pic_height_in_ctb * 6)+15) & (-16)) » 3
Eq. ensures
multiple of 2
Current and Collocated
Motion Vector Temporal
Buffer (lcu=16x16)
(((picture_width_in_pixels+63)»6)*((picture_height_in_pixels+15)»4)
Eq. ensures
multiple of 2
Current and Collocated
Motion Vector Temporal
Buffer (lcu>16x16)
(((picture_width_in_pixels+31)»5)*((picture_height_in_pixels+31)»5)
Eq. ensures
multiple of 2
SSE Line Buffer
(Picture_width_in_lcu + 2) « 4
HEVC 10 bit Buffer Size Requirements
Buffer Name
Minimum Size in CLs
Notes
Deblocking Filter Line Buffer
((picture_width_in_pixels + 31) & (-32)) » 2
Eq. ensures
multiple of 4
Deblocking Filter Tile Line
Buffer
((picture_width_in_pixels + 31) & (-32)) » 2
Eq. ensures
multiple of 4
Deblocking Filter Tile
Column Buffer
((picture_height_in_pixels + 6*pic_height_in_ctb + 31) & (-32)) » 2
Eq. ensures
multiple of 4
Metadata Line Buffer (all
intra slices)
(picture_width_in_pixels + pic_width_in_lcu*8 + 1023) » 9
Eq. ensures
multiple of 2
Metadata Tile Line Buffer (all
intra slices)
(picture_width_in_pixels + pic_width_in_lcu *8 + 1023) » 9
Eq. ensures
multiple of 2
Metadata Tile Column Buffer
(all intra slices)
(picture_height_in_pixels + picture_height_in_lcu * 16 + 1023) » 9
Eq. ensures
multiple of 2
Metadata Line Buffer (some
inter slices)
(((picture_width_in_pixels+15)»4)*188 + pic_width_in_lcu*9 + 1023) » 9
Eq. ensures
multiple of 2
Metadata Tile Line Buffer
(some inter slices)
(((picture_width_in_pixels +15)»4)*172 + pic_width_in_lcu *9 + 1023) »
9
Eq. ensures
multiple of 2
Metadata Tile Column Buffer
(some inter slices)
(((picture_height_in_pixels +15)»4)*176 + picture_height_in_lcu * 89 +
1023) » 9
Eq. ensures
multiple of 2
SAO Line Buffer
(((picture_width_in_pixels » 1) + pic_width_in_ctb * 3)+15) & (-16)) » 2
Eq. ensures
multiple of 2
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
13
Buffer Name
Minimum Size in CLs
Notes
SAO Tile Line Buffer
(((picture_width_in_pixels » 1) + picture_width_in_ctb * 6)+15) & (-16))
» 2
Eq. ensures
multiple of 2
SAO Tile Column Buffer
(((picture_height_in_pixels » 1) + pic_height_in_ctb * 6)+15) & (-16)) »
2
Eq. ensures
multiple of 2
Current and Collocated
Motion Vector Temporal
Buffer (lcu=16x16)
(((picture_width_in_pixels+63)»6)*((picture_height_in_pixels+15)»4)
Eq. ensures
multiple of 2
Current and Collocated
Motion Vector Temporal
Buffer (lcu>16x16)
(((picture_width_in_pixels+31)»5)*((picture_height_in_pixels+31)»5)
Eq. ensures
multiple of 2
SSE Line Buffer
(Picture_width_in_lcu + 2) « 4
Internal Media Rowstore Table
If the internal Media Rowstore exists, driver should use the storage as the following table indicates.
HEVC Pipeline
Frame Width
DAT
DF
SAO
DAT Addr
DF Addr
SAO Addr
HEVC
<= 2048
Y
Y
Y
0
64
320
2048 < x <= 4096
Y
Y
N
0
128
N/A
4096 < x <=8196
Y
N
N
0
N/A
N/A
VP9 Common Commands
Commands
HCP_PIPE_MODE_SELECT
HCP_SURFACE_STATE
HCP_PIPE_BUF_ADDR_STATE
HCP_IND_OBJ_BASE_ADDR_STATE
HCP_VP9_SEGMENT_STATE
HCP_VP9_PIC_STATE
HCP Common Commands
HCP_PIC_STATE (VideoCS)
HCP_TILE_STATE (VideoCS)
HCP_REF_IDX_STATE (VideoCS)
HCP_WEIGHTOFFSET_STATE (VideoCS)
HCP_SLICE_STATE (VideoCS)
HEVC_VP9_RDOQ_STATE
HEVC
14
Doc Ref # IHD-OS-KBL-Vol 10-1.17
VP9 Commands
HCP_BSD_OBJECT (triggers HW start)
HCP_VP9_PAK_OBJECT
Tile Size and CU Stream-out Records
CU statistics record (individual PUs per record down to 8x8 only) (Note: For Advanced BRC but not
supported in HW yet)
Fields
Bits
Skip
3:0
Indicates Skip flag
Group 4 4x4s -> 4 bits
InterMode
11:4
InterMode:
0 NEARESTMV, 1 NEARMV, 2 ZEROMV, 3NEWMV
Group 4 4x4s total 8 bits
Reserved
15:12
NZ coeff count
28:16
Number of non-zero coeffs; sum of YUV, 13bits
Reserved
31:29
NumBitsforCoeffs
47:32
Number of Bits for coefficients per block, 16bits
NumBitsforBlock
63:48
Number of Bits in block
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
1
Stream-in Probability Table
In Encoder mode, two sets of this table will be streamed out: one for the current frame probability update and one for future frame.
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
CL
aligned
0
1
tx_probs_8x8
[0] [0..0]
100
10
0
0
0
0
0
MODE COUNTERS
(counts tx)
0-17
1
1
tx_probs_8x8
[1] [0..0]
66
66
0
1
1
2
2
tx_probs_16x16
[0] [0..1]
20, 152
20,
15
2
0
2
2
4
2
tx_probs_16x16
[1] [0..1]
15, 101
15,
10
1
0
4
4
6
3
tx_probs_32x32
[0] [0..2]
3, 136,
37
3,
13
6,
37
0
6
6
9
3
tx_probs_32x32
[1] [0..2]
5, 52,
13
5,
52,
13
0
9
9
12
52
DUMMY
0, 0, 0,
0
0,
0,
0,
0
52
12
CL
aligned
64
3
coef_probs_4x4
[0] [0] [0] [0]
195,
29, 183
19
5,
0
12
8
COEFF COUNTERS
(coeff_count_mod
0-
28
HEVC
2
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0..2]
29,
18
3
el_coeff)
7
67
3
coef_probs_4x4
[0] [0] [0] [1]
[0..2]
84, 49,
136
84,
49,
13
6
0
15
70
3
coef_probs_4x4
[0] [0] [0] [2]
[0..2]
8, 42,
71
8,
42,
71
0
18
73
3
coef_probs_4x4
[0] [0] [1] [0]
[0..2]
31,
107,
169
31,
10
7,
16
9
0
21
76
3
coef_probs_4x4
[0] [0] [1] [1]
[0..2]
35, 99,
159
35,
99,
15
9
0
24
79
3
coef_probs_4x4
[0] [0] [1] [2]
[0..2]
17, 82,
140
17,
82,
14
0
0
27
82
3
coef_probs_4x4
[0] [0] [1] [3]
[0..2]
8, 66,
114
8,
66,
11
0
30
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
3
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
4
85
3
coef_probs_4x4
[0] [0] [1] [4]
[0..2]
2, 44,
76
2,
44,
76
0
33
88
3
coef_probs_4x4
[0] [0] [1] [5]
[0..2]
1, 19,
32
1,
19,
32
0
36
91
3
coef_probs_4x4
[0] [0] [2] [0]
[0..2]
40,
132,
201
40,
13
2,
20
1
0
39
94
3
coef_probs_4x4
[0] [0] [2] [1]
[0..2]
29,
114,
187
29,
11
4,
18
7
0
42
97
3
coef_probs_4x4
[0] [0] [2] [2]
[0..2]
13, 91,
157
13,
91,
15
7
0
45
100
3
coef_probs_4x4
[0] [0] [2] [3]
[0..2]
7, 75,
127
7,
75,
12
7
0
48
103
3
coef_probs_4x4
3, 58,
3,
0
51
HEVC
4
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0] [0] [2] [4]
[0..2]
95
58,
95
106
3
coef_probs_4x4
[0] [0] [2] [5]
[0..2]
1, 28,
47
1,
28,
47
0
54
109
3
coef_probs_4x4
[0] [0] [3] [0]
[0..2]
69,
142,
221
69,
14
2,
22
1
0
57
112
3
coef_probs_4x4
[0] [0] [3] [1]
[0..2]
42,
122,
201
42,
12
2,
20
1
0
60
115
3
coef_probs_4x4
[0] [0] [3] [2]
[0..2]
15, 91,
159
15,
91,
15
9
0
63
118
3
coef_probs_4x4
[0] [0] [3] [3]
[0..2]
6, 67,
121
6,
67,
12
1
0
66
121
3
coef_probs_4x4
[0] [0] [3] [4]
[0..2]
1, 42,
77
1,
42,
77
0
69
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
5
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
124
3
coef_probs_4x4
[0] [0] [3] [5]
[0..2]
1, 17,
31
1,
17,
31
0
72
127
3
coef_probs_4x4
[0] [0] [4] [0]
[0..2]
102,
148,
228
10
2,
14
8,
22
8
0
75
130
3
coef_probs_4x4
[0] [0] [4] [1]
[0..2]
67,
117,
204
67,
11
7,
20
4
0
78
133
3
coef_probs_4x4
[0] [0] [4] [2]
[0..2]
17, 82,
154
17,
82,
15
4
0
81
136
3
coef_probs_4x4
[0] [0] [4] [3]
[0..2]
6, 59,
114
6,
59,
11
4
0
84
139
3
coef_probs_4x4
[0] [0] [4] [4]
[0..2]
2, 39,
75
2,
39,
75
0
87
142
3
coef_probs_4x4
1, 15,
1,
0
90
HEVC
6
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0] [0] [4] [5]
[0..2]
29
15,
29
145
3
coef_probs_4x4
[0] [0] [5] [0]
[0..2]
156,
57, 233
15
6,
57,
23
3
0
93
148
3
coef_probs_4x4
[0] [0] [5] [1]
[0..2]
119,
57, 212
11
9,
57,
21
2
0
96
151
3
coef_probs_4x4
[0] [0] [5] [2]
[0..2]
58, 48,
163
58,
48,
16
3
0
99
154
3
coef_probs_4x4
[0] [0] [5] [3]
[0..2]
29, 40,
124
29,
40,
12
4
0
10
2
157
3
coef_probs_4x4
[0] [0] [5] [4]
[0..2]
12, 30,
81
12,
30,
81
0
10
5
160
3
coef_probs_4x4
[0] [0] [5] [5]
[0..2]
3, 12,
31
3,
12,
31
0
10
8
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
7
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
163
3
coef_probs_4x4
[0] [1] [0] [0]
[0..2]
191,
107,
226
19
1,
10
7,
22
6
0
11
1
166
3
coef_probs_4x4
[0] [1] [0] [1]
[0..2]
124,
117,
204
12
4,
11
7,
20
4
0
11
4
169
3
coef_probs_4x4
[0] [1] [0] [2]
[0..2]
25, 99,
155
25,
99,
15
5
0
11
7
172
3
coef_probs_4x4
[0] [1] [1] [0]
[0..2]
29,
148,
210
29,
14
8,
21
0
0
12
0
175
3
coef_probs_4x4
[0] [1] [1] [1]
[0..2]
37,
126,
194
37,
12
6,
19
4
0
12
3
178
3
coef_probs_4x4
8, 93,
8,
0
12
HEVC
8
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0] [1] [1] [2]
[0..2]
157
93,
15
7
6
181
3
coef_probs_4x4
[0] [1] [1] [3]
[0..2]
2, 68,
118
2,
68,
11
8
0
12
9
184
3
coef_probs_4x4
[0] [1] [1] [4]
[0..2]
1, 39,
69
1,
39,
69
0
13
2
187
3
coef_probs_4x4
[0] [1] [1] [5]
[0..2]
1, 17,
33
1,
17,
33
0
13
5
190
3
coef_probs_4x4
[0] [1] [2] [0]
[0..2]
41,
151,
213
41,
15
1,
21
3
0
13
8
193
3
coef_probs_4x4
[0] [1] [2] [1]
[0..2]
27,
123,
193
27,
12
3,
19
3
0
14
1
196
3
coef_probs_4x4
[0] [1] [2] [2]
[0..2]
3, 82,
144
3,
82,
14
0
14
4
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
9
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
4
199
3
coef_probs_4x4
[0] [1] [2] [3]
[0..2]
1, 58,
105
1,
58,
10
5
0
14
7
202
3
coef_probs_4x4
[0] [1] [2] [4]
[0..2]
1, 32,
60
1,
32,
60
0
15
0
205
3
coef_probs_4x4
[0] [1] [2] [5]
[0..2]
1, 13,
26
1,
13,
26
0
15
3
208
3
coef_probs_4x4
[0] [1] [3] [0]
[0..2]
59,
159,
220
59,
15
9,
22
0
0
15
6
211
3
coef_probs_4x4
[0] [1] [3] [1]
[0..2]
23,
126,
198
23,
12
6,
19
8
0
15
9
214
3
coef_probs_4x4
[0] [1] [3] [2]
[0..2]
4, 88,
151
4,
88,
15
1
0
16
2
217
3
coef_probs_4x4
1, 66,
1,
0
16
HEVC
10
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0] [1] [3] [3]
[0..2]
114
66,
11
4
5
220
3
coef_probs_4x4
[0] [1] [3] [4]
[0..2]
1, 38,
71
1,
38,
71
0
16
8
223
3
coef_probs_4x4
[0] [1] [3] [5]
[0..2]
1, 18,
34
1,
18,
34
0
17
1
226
3
coef_probs_4x4
[0] [1] [4] [0]
[0..2]
114,
136,
232
11
4,
13
6,
23
2
0
17
4
229
3
coef_probs_4x4
[0] [1] [4] [1]
[0..2]
51,
114,
207
51,
11
4,
20
7
0
17
7
232
3
coef_probs_4x4
[0] [1] [4] [2]
[0..2]
11, 83,
155
11,
83,
15
5
0
18
0
235
3
coef_probs_4x4
[0] [1] [4] [3]
3, 56,
105
3,
56,
0
18
3
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
11
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0..2]
10
5
238
3
coef_probs_4x4
[0] [1] [4] [4]
[0..2]
1, 33,
65
1,
33,
65
0
18
6
241
3
coef_probs_4x4
[0] [1] [4] [5]
[0..2]
1, 17,
34
1,
17,
34
0
18
9
244
3
coef_probs_4x4
[0] [1] [5] [0]
[0..2]
149,
65, 234
14
9,
65,
23
4
0
19
2
247
3
coef_probs_4x4
[0] [1] [5] [1]
[0..2]
121,
57, 215
12
1,
57,
21
5
0
19
5
250
3
coef_probs_4x4
[0] [1] [5] [2]
[0..2]
61, 49,
166
61,
49,
16
6
0
19
8
253
3
coef_probs_4x4
[0] [1] [5] [3]
[0..2]
28, 36,
114
28,
36,
11
4
0
20
1
HEVC
12
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
256
3
coef_probs_4x4
[0] [1] [5] [4]
[0..2]
12, 25,
76
12,
25,
76
0
20
4
259
3
coef_probs_4x4
[0] [1] [5] [5]
[0..2]
3, 16,
42
3,
16,
42
0
20
7
262
3
coef_probs_4x4
[1] [0] [0] [0]
[0..2]
214,
49, 220
21
4,
49,
22
0
0
21
0
0-287
265
3
coef_probs_4x4
[1] [0] [0] [1]
[0..2]
132,
63, 188
13
2,
63,
18
8
0
21
3
268
3
coef_probs_4x4
[1] [0] [0] [2]
[0..2]
42, 65,
137
42,
65,
13
7
0
21
6
271
3
coef_probs_4x4
[1] [0] [1] [0]
[0..2]
85,
137,
221
85,
13
7,
22
1
0
21
9
274
3
coef_probs_4x4
104,
10
0
22
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
13
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[1] [0] [1] [1]
[0..2]
131,
216
4,
13
1,
21
6
2
277
3
coef_probs_4x4
[1] [0] [1] [2]
[0..2]
49,
111,
192
49,
11
1,
19
2
0
22
5
280
3
coef_probs_4x4
[1] [0] [1] [3]
[0..2]
21, 87,
155
21,
87,
15
5
0
22
8
283
3
coef_probs_4x4
[1] [0] [1] [4]
[0..2]
2, 49,
87
2,
49,
87
0
23
1
286
3
coef_probs_4x4
[1] [0] [1] [5]
[0..2]
1, 16,
28
1,
16,
28
0
23
4
289
3
coef_probs_4x4
[1] [0] [2] [0]
[0..2]
89,
163,
230
89,
16
3,
23
0
0
23
7
292
3
coef_probs_4x4
90,
90,
0
24
HEVC
14
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[1] [0] [2] [1]
[0..2]
137,
220
13
7,
22
0
0
295
3
coef_probs_4x4
[1] [0] [2] [2]
[0..2]
29,
100,
183
29,
10
0,
18
3
0
24
3
298
3
coef_probs_4x4
[1] [0] [2] [3]
[0..2]
10, 70,
135
10,
70,
13
5
0
24
6
301
3
coef_probs_4x4
[1] [0] [2] [4]
[0..2]
2, 42,
81
2,
42,
81
0
24
9
304
3
coef_probs_4x4
[1] [0] [2] [5]
[0..2]
1, 17,
33
1,
17,
33
0
25
2
307
3
coef_probs_4x4
[1] [0] [3] [0]
[0..2]
108,
167,
237
10
8,
16
7,
23
7
0
25
5
310
3
coef_probs_4x4
55,
55,
0
25
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
15
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[1] [0] [3] [1]
[0..2]
133,
222
13
3,
22
2
8
313
3
coef_probs_4x4
[1] [0] [3] [2]
[0..2]
15, 97,
179
15,
97,
17
9
0
26
1
316
3
coef_probs_4x4
[1] [0] [3] [3]
[0..2]
4, 72,
135
4,
72,
13
5
0
26
4
319
3
coef_probs_4x4
[1] [0] [3] [4]
[0..2]
1, 45,
85
1,
45,
85
0
26
7
322
3
coef_probs_4x4
[1] [0] [3] [5]
[0..2]
1, 19,
38
1,
19,
38
0
27
0
325
3
coef_probs_4x4
[1] [0] [4] [0]
[0..2]
124,
146,
240
12
4,
14
6,
24
0
0
27
3
328
3
coef_probs_4x4
[1] [0] [4] [1]
66,
124,
66,
12
0
27
6
HEVC
16
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0..2]
224
4,
22
4
331
3
coef_probs_4x4
[1] [0] [4] [2]
[0..2]
17, 88,
175
17,
88,
17
5
0
27
9
334
3
coef_probs_4x4
[1] [0] [4] [3]
[0..2]
4, 58,
122
4,
58,
12
2
0
28
2
337
3
coef_probs_4x4
[1] [0] [4] [4]
[0..2]
1, 36,
75
1,
36,
75
0
28
5
340
3
coef_probs_4x4
[1] [0] [4] [5]
[0..2]
1, 18,
37
1,
18,
37
0
28
8
343
3
coef_probs_4x4
[1] [0] [5] [0]
[0..2]
141,
79, 241
14
1,
79,
24
1
0
29
1
346
3
coef_probs_4x4
[1] [0] [5] [1]
[0..2]
126,
70, 227
12
6,
70,
22
0
29
4
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
7
349
3
coef_probs_4x4
[1] [0] [5] [2]
[0..2]
66, 58,
182
66,
58,
18
2
0
29
7
352
3
coef_probs_4x4
[1] [0] [5] [3]
[0..2]
30, 44,
136
30,
44,
13
6
0
30
0
355
3
coef_probs_4x4
[1] [0] [5] [4]
[0..2]
12, 34,
96
12,
34,
96
0
30
3
358
3
coef_probs_4x4
[1] [0] [5] [5]
[0..2]
2, 20,
47
2,
20,
47
0
30
6
361
3
coef_probs_4x4
[1] [1] [0] [0]
[0..2]
229,
99, 249
22
9,
99,
24
9
0
30
9
364
3
coef_probs_4x4
[1] [1] [0] [1]
[0..2]
143,
111,
235
14
3,
11
1,
23
5
0
31
2
HEVC
18
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
367
3
coef_probs_4x4
[1] [1] [0] [2]
[0..2]
46,
109,
192
46,
10
9,
19
2
0
31
5
370
3
coef_probs_4x4
[1] [1] [1] [0]
[0..2]
82,
158,
236
82,
15
8,
23
6
0
31
8
373
3
coef_probs_4x4
[1] [1] [1] [1]
[0..2]
94,
146,
224
94,
14
6,
22
4
0
32
1
376
3
coef_probs_4x4
[1] [1] [1] [2]
[0..2]
25,
117,
191
25,
11
7,
19
1
0
32
4
379
3
coef_probs_4x4
[1] [1] [1] [3]
[0..2]
9, 87,
149
9,
87,
14
9
0
32
7
382
3
coef_probs_4x4
[1] [1] [1] [4]
[0..2]
3, 56,
99
3,
56,
99
0
33
0
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
19
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
385
3
coef_probs_4x4
[1] [1] [1] [5]
[0..2]
1, 33,
57
1,
33,
57
0
33
3
388
3
coef_probs_4x4
[1] [1] [2] [0]
[0..2]
83,
167,
237
83,
16
7,
23
7
0
33
6
391
3
coef_probs_4x4
[1] [1] [2] [1]
[0..2]
68,
145,
222
68,
14
5,
22
2
0
33
9
394
3
coef_probs_4x4
[1] [1] [2] [2]
[0..2]
10,
103,
177
10,
10
3,
17
7
0
34
2
397
3
coef_probs_4x4
[1] [1] [2] [3]
[0..2]
2, 72,
131
2,
72,
13
1
0
34
5
400
3
coef_probs_4x4
[1] [1] [2] [4]
[0..2]
1, 41,
79
1,
41,
79
0
34
8
403
3
coef_probs_4x4
1, 20,
1,
0
35
HEVC
20
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[1] [1] [2] [5]
[0..2]
39
20,
39
1
406
3
coef_probs_4x4
[1] [1] [3] [0]
[0..2]
99,
167,
239
99,
16
7,
23
9
0
35
4
409
3
coef_probs_4x4
[1] [1] [3] [1]
[0..2]
47,
141,
224
47,
14
1,
22
4
0
35
7
412
3
coef_probs_4x4
[1] [1] [3] [2]
[0..2]
10,
104,
178
10,
10
4,
17
8
0
36
0
415
3
coef_probs_4x4
[1] [1] [3] [3]
[0..2]
2, 73,
133
2,
73,
13
3
0
36
3
418
3
coef_probs_4x4
[1] [1] [3] [4]
[0..2]
1, 44,
85
1,
44,
85
0
36
6
421
3
coef_probs_4x4
[1] [1] [3] [5]
1, 22,
47
1,
22,
0
36
9
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
21
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0..2]
47
424
3
coef_probs_4x4
[1] [1] [4] [0]
[0..2]
127,
145,
243
12
7,
14
5,
24
3
0
37
2
427
3
coef_probs_4x4
[1] [1] [4] [1]
[0..2]
71,
129,
228
71,
12
9,
22
8
0
37
5
430
3
coef_probs_4x4
[1] [1] [4] [2]
[0..2]
17, 93,
177
17,
93,
17
7
0
37
8
433
3
coef_probs_4x4
[1] [1] [4] [3]
[0..2]
3, 61,
124
3,
61,
12
4
0
38
1
436
3
coef_probs_4x4
[1] [1] [4] [4]
[0..2]
1, 41,
84
1,
41,
84
0
38
4
439
3
coef_probs_4x4
[1] [1] [4] [5]
[0..2]
1, 21,
52
1,
21,
52
0
38
7
HEVC
22
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
442
3
coef_probs_4x4
[1] [1] [5] [0]
[0..2]
157,
78, 244
15
7,
78,
24
4
0
39
0
445
3
coef_probs_4x4
[1] [1] [5] [1]
[0..2]
140,
72, 231
14
0,
72,
23
1
0
39
3
448
3
coef_probs_4x4
[1] [1] [5] [2]
[0..2]
69, 58,
184
69,
58,
18
4
0
39
6
451
3
coef_probs_4x4
[1] [1] [5] [3]
[0..2]
31, 44,
137
31,
44,
13
7
0
39
9
454
3
coef_probs_4x4
[1] [1] [5] [4]
[0..2]
14, 38,
105
14,
38,
10
5
0
40
2
457
3
coef_probs_4x4
[1] [1] [5] [5]
[0..2]
8, 23,
61
8,
23,
61
0
40
5
460
3
coef_probs_8x8
125,
12
0
40
57.
0-
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
23
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0] [0] [0] [0]
[0..2]
34, 187
5,
34,
18
7
8
5
28
7
463
3
coef_probs_8x8
[0] [0] [0] [1]
[0..2]
52, 41,
133
52,
41,
13
3
0
41
1
466
3
coef_probs_8x8
[0] [0] [0] [2]
[0..2]
6, 31,
56
6,
31,
56
0
41
4
469
3
coef_probs_8x8
[0] [0] [1] [0]
[0..2]
37,
109,
153
37,
10
9,
15
3
0
41
7
472
3
coef_probs_8x8
[0] [0] [1] [1]
[0..2]
51,
102,
147
51,
10
2,
14
7
0
42
0
475
3
coef_probs_8x8
[0] [0] [1] [2]
[0..2]
23, 87,
128
23,
87,
12
8
0
42
3
478
3
coef_probs_8x8
8, 67,
8,
0
42
HEVC
24
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0] [0] [1] [3]
[0..2]
101
67,
10
1
6
481
3
coef_probs_8x8
[0] [0] [1] [4]
[0..2]
1, 41,
63
1,
41,
63
0
42
9
484
3
coef_probs_8x8
[0] [0] [1] [5]
[0..2]
1, 19,
29
1,
19,
29
0
43
2
487
3
coef_probs_8x8
[0] [0] [2] [0]
[0..2]
31,
154,
185
31,
15
4,
18
5
0
43
5
490
3
coef_probs_8x8
[0] [0] [2] [1]
[0..2]
17,
127,
175
17,
12
7,
17
5
0
43
8
493
3
coef_probs_8x8
[0] [0] [2] [2]
[0..2]
6, 96,
145
6,
96,
14
5
0
44
1
496
3
coef_probs_8x8
[0] [0] [2] [3]
[0..2]
2, 73,
114
2,
73,
11
0
44
4
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
25
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
4
499
3
coef_probs_8x8
[0] [0] [2] [4]
[0..2]
1, 51,
82
1,
51,
82
0
44
7
502
3
coef_probs_8x8
[0] [0] [2] [5]
[0..2]
1, 28,
45
1,
28,
45
0
45
0
505
3
coef_probs_8x8
[0] [0] [3] [0]
[0..2]
23,
163,
200
23,
16
3,
20
0
0
45
3
508
3
coef_probs_8x8
[0] [0] [3] [1]
[0..2]
10,
131,
185
10,
13
1,
18
5
0
45
6
511
3
coef_probs_8x8
[0] [0] [3] [2]
[0..2]
2, 93,
148
2,
93,
14
8
0
45
9
514
3
coef_probs_8x8
[0] [0] [3] [3]
[0..2]
1, 67,
111
1,
67,
11
1
0
46
2
517
3
coef_probs_8x8
1, 41,
1,
0
46
HEVC
26
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0] [0] [3] [4]
[0..2]
69
41,
69
5
520
3
coef_probs_8x8
[0] [0] [3] [5]
[0..2]
1, 14,
24
1,
14,
24
0
46
8
523
3
coef_probs_8x8
[0] [0] [4] [0]
[0..2]
29,
176,
217
29,
17
6,
21
7
0
47
1
526
3
coef_probs_8x8
[0] [0] [4] [1]
[0..2]
12,
145,
201
12,
14
5,
20
1
0
47
4
529
3
coef_probs_8x8
[0] [0] [4] [2]
[0..2]
3, 101,
156
3,
10
1,
15
6
0
47
7
532
3
coef_probs_8x8
[0] [0] [4] [3]
[0..2]
1, 69,
111
1,
69,
11
1
0
48
0
535
3
coef_probs_8x8
[0] [0] [4] [4]
1, 39,
63
1,
39,
0
48
3
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
27
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0..2]
63
538
3
coef_probs_8x8
[0] [0] [4] [5]
[0..2]
1, 14,
23
1,
14,
23
0
48
6
541
3
coef_probs_8x8
[0] [0] [5] [0]
[0..2]
57,
192,
233
57,
19
2,
23
3
0
48
9
544
3
coef_probs_8x8
[0] [0] [5] [1]
[0..2]
25,
154,
215
25,
15
4,
21
5
0
49
2
547
3
coef_probs_8x8
[0] [0] [5] [2]
[0..2]
6, 109,
167
6,
10
9,
16
7
0
49
5
550
3
coef_probs_8x8
[0] [0] [5] [3]
[0..2]
3, 78,
118
3,
78,
11
8
0
49
8
553
3
coef_probs_8x8
[0] [0] [5] [4]
[0..2]
1, 48,
69
1,
48,
69
0
50
1
HEVC
28
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
556
3
coef_probs_8x8
[0] [0] [5] [5]
[0..2]
1, 21,
29
1,
21,
29
0
50
4
559
3
coef_probs_8x8
[0] [1] [0] [0]
[0..2]
202,
105,
245
20
2,
10
5,
24
5
0
50
7
562
3
coef_probs_8x8
[0] [1] [0] [1]
[0..2]
108,
106,
216
10
8,
10
6,
21
6
0
51
0
565
3
coef_probs_8x8
[0] [1] [0] [2]
[0..2]
18, 90,
144
18,
90,
14
4
0
51
3
568
3
coef_probs_8x8
[0] [1] [1] [0]
[0..2]
33,
172,
219
33,
17
2,
21
9
0
51
6
571
3
coef_probs_8x8
[0] [1] [1] [1]
[0..2]
64,
149,
206
64,
14
9,
0
51
9
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
29
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
20
6
574
3
coef_probs_8x8
[0] [1] [1] [2]
[0..2]
14,
117,
177
14,
11
7,
17
7
0
52
2
577
3
coef_probs_8x8
[0] [1] [1] [3]
[0..2]
5, 90,
141
5,
90,
14
1
0
52
5
580
3
coef_probs_8x8
[0] [1] [1] [4]
[0..2]
2, 61,
95
2,
61,
95
0
52
8
583
3
coef_probs_8x8
[0] [1] [1] [5]
[0..2]
1, 37,
57
1,
37,
57
0
53
1
586
3
coef_probs_8x8
[0] [1] [2] [0]
[0..2]
33,
179,
220
33,
17
9,
22
0
0
53
4
589
3
coef_probs_8x8
[0] [1] [2] [1]
[0..2]
11,
140,
198
11,
14
0,
19
0
53
7
HEVC
30
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
8
592
3
coef_probs_8x8
[0] [1] [2] [2]
[0..2]
1, 89,
148
1,
89,
14
8
0
54
0
595
3
coef_probs_8x8
[0] [1] [2] [3]
[0..2]
1, 60,
104
1,
60,
10
4
0
54
3
598
3
coef_probs_8x8
[0] [1] [2] [4]
[0..2]
1, 33,
57
1,
33,
57
0
54
6
601
3
coef_probs_8x8
[0] [1] [2] [5]
[0..2]
1, 12,
21
1,
12,
21
0
54
9
604
3
coef_probs_8x8
[0] [1] [3] [0]
[0..2]
30,
181,
221
30,
18
1,
22
1
0
55
2
607
3
coef_probs_8x8
[0] [1] [3] [1]
[0..2]
8, 141,
198
8,
14
1,
19
8
0
55
5
610
3
coef_probs_8x8
1, 87,
1,
0
55
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
31
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0] [1] [3] [2]
[0..2]
145
87,
14
5
8
613
3
coef_probs_8x8
[0] [1] [3] [3]
[0..2]
1, 58,
100
1,
58,
10
0
0
56
1
616
3
coef_probs_8x8
[0] [1] [3] [4]
[0..2]
1, 31,
55
1,
31,
55
0
56
4
619
3
coef_probs_8x8
[0] [1] [3] [5]
[0..2]
1, 12,
20
1,
12,
20
0
56
7
622
3
coef_probs_8x8
[0] [1] [4] [0]
[0..2]
32,
186,
224
32,
18
6,
22
4
0
57
0
625
3
coef_probs_8x8
[0] [1] [4] [1]
[0..2]
7, 142,
198
7,
14
2,
19
8
0
57
3
628
3
coef_probs_8x8
[0] [1] [4] [2]
[0..2]
1, 86,
143
1,
86,
14
0
57
6
HEVC
32
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
3
631
3
coef_probs_8x8
[0] [1] [4] [3]
[0..2]
1, 58,
100
1,
58,
10
0
0
57
9
634
3
coef_probs_8x8
[0] [1] [4] [4]
[0..2]
1, 31,
55
1,
31,
55
0
58
2
637
3
coef_probs_8x8
[0] [1] [4] [5]
[0..2]
1, 12,
22
1,
12,
22
0
58
5
640
3
coef_probs_8x8
[0] [1] [5] [0]
[0..2]
57,
192,
227
57,
19
2,
22
7
0
58
8
643
3
coef_probs_8x8
[0] [1] [5] [1]
[0..2]
20,
143,
204
20,
14
3,
20
4
0
59
1
646
3
coef_probs_8x8
[0] [1] [5] [2]
[0..2]
3, 96,
154
3,
96,
15
4
0
59
4
649
3
coef_probs_8x8
1, 68,
1,
0
59
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
33
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0] [1] [5] [3]
[0..2]
112
68,
11
2
7
652
3
coef_probs_8x8
[0] [1] [5] [4]
[0..2]
1, 42,
69
1,
42,
69
0
60
0
655
3
coef_probs_8x8
[0] [1] [5] [5]
[0..2]
1, 19,
32
1,
19,
32
0
60
3
658
3
coef_probs_8x8
[1] [0] [0] [0]
[0..2]
212,
35, 215
21
2,
35,
21
5
0
60
6
0-287
661
3
coef_probs_8x8
[1] [0] [0] [1]
[0..2]
113,
47, 169
11
3,
47,
16
9
0
60
9
664
3
coef_probs_8x8
[1] [0] [0] [2]
[0..2]
29, 48,
105
29,
48,
10
5
0
61
2
667
3
coef_probs_8x8
[1] [0] [1] [0]
[0..2]
74,
129,
203
74,
12
9,
0
61
5
HEVC
34
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
20
3
670
3
coef_probs_8x8
[1] [0] [1] [1]
[0..2]
106,
120,
203
10
6,
12
0,
20
3
0
61
8
673
3
coef_probs_8x8
[1] [0] [1] [2]
[0..2]
49,
107,
178
49,
10
7,
17
8
0
62
1
676
3
coef_probs_8x8
[1] [0] [1] [3]
[0..2]
19, 84,
144
19,
84,
14
4
0
62
4
679
3
coef_probs_8x8
[1] [0] [1] [4]
[0..2]
4, 50,
84
4,
50,
84
0
62
7
682
3
coef_probs_8x8
[1] [0] [1] [5]
[0..2]
1, 15,
25
1,
15,
25
0
63
0
685
3
coef_probs_8x8
[1] [0] [2] [0]
[0..2]
71,
172,
217
71,
17
2,
0
63
3
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
35
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
21
7
688
3
coef_probs_8x8
[1] [0] [2] [1]
[0..2]
44,
141,
209
44,
14
1,
20
9
0
63
6
691
3
coef_probs_8x8
[1] [0] [2] [2]
[0..2]
15,
102,
173
15,
10
2,
17
3
0
63
9
694
3
coef_probs_8x8
[1] [0] [2] [3]
[0..2]
6, 76,
133
6,
76,
13
3
0
64
2
697
3
coef_probs_8x8
[1] [0] [2] [4]
[0..2]
2, 51,
89
2,
51,
89
0
64
5
700
3
coef_probs_8x8
[1] [0] [2] [5]
[0..2]
1, 24,
42
1,
24,
42
0
64
8
703
3
coef_probs_8x8
[1] [0] [3] [0]
[0..2]
64,
185,
231
64,
18
5,
23
0
65
1
HEVC
36
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
1
706
3
coef_probs_8x8
[1] [0] [3] [1]
[0..2]
31,
148,
216
31,
14
8,
21
6
0
65
4
709
3
coef_probs_8x8
[1] [0] [3] [2]
[0..2]
8, 103,
175
8,
10
3,
17
5
0
65
7
712
3
coef_probs_8x8
[1] [0] [3] [3]
[0..2]
3, 74,
131
3,
74,
13
1
0
66
0
715
3
coef_probs_8x8
[1] [0] [3] [4]
[0..2]
1, 46,
81
1,
46,
81
0
66
3
718
3
coef_probs_8x8
[1] [0] [3] [5]
[0..2]
1, 18,
30
1,
18,
30
0
66
6
721
3
coef_probs_8x8
[1] [0] [4] [0]
[0..2]
65,
196,
235
65,
19
6,
23
5
0
66
9
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
37
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
724
3
coef_probs_8x8
[1] [0] [4] [1]
[0..2]
25,
157,
221
25,
15
7,
22
1
0
67
2
727
3
coef_probs_8x8
[1] [0] [4] [2]
[0..2]
5, 105,
174
5,
10
5,
17
4
0
67
5
730
3
coef_probs_8x8
[1] [0] [4] [3]
[0..2]
1, 67,
120
1,
67,
12
0
0
67
8
733
3
coef_probs_8x8
[1] [0] [4] [4]
[0..2]
1, 38,
69
1,
38,
69
0
68
1
736
3
coef_probs_8x8
[1] [0] [4] [5]
[0..2]
1, 15,
30
1,
15,
30
0
68
4
739
3
coef_probs_8x8
[1] [0] [5] [0]
[0..2]
65,
204,
238
65,
20
4,
23
8
0
68
7
742
3
coef_probs_8x8
30,
30,
0
69
HEVC
38
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[1] [0] [5] [1]
[0..2]
156,
224
15
6,
22
4
0
745
3
coef_probs_8x8
[1] [0] [5] [2]
[0..2]
7, 107,
177
7,
10
7,
17
7
0
69
3
748
3
coef_probs_8x8
[1] [0] [5] [3]
[0..2]
2, 70,
124
2,
70,
12
4
0
69
6
751
3
coef_probs_8x8
[1] [0] [5] [4]
[0..2]
1, 42,
73
1,
42,
73
0
69
9
754
3
coef_probs_8x8
[1] [0] [5] [5]
[0..2]
1, 18,
34
1,
18,
34
0
70
2
757
3
coef_probs_8x8
[1] [1] [0] [0]
[0..2]
225,
86, 251
22
5,
86,
25
1
0
70
5
760
3
coef_probs_8x8
[1] [1] [0] [1]
144,
104,
14
4,
0
70
8
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
39
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0..2]
235
10
4,
23
5
763
3
coef_probs_8x8
[1] [1] [0] [2]
[0..2]
42, 99,
181
42,
99,
18
1
0
71
1
766
3
coef_probs_8x8
[1] [1] [1] [0]
[0..2]
85,
175,
239
85,
17
5,
23
9
0
71
4
769
3
coef_probs_8x8
[1] [1] [1] [1]
[0..2]
112,
165,
229
11
2,
16
5,
22
9
0
71
7
772
3
coef_probs_8x8
[1] [1] [1] [2]
[0..2]
29,
136,
200
29,
13
6,
20
0
0
72
0
775
3
coef_probs_8x8
[1] [1] [1] [3]
[0..2]
12,
103,
162
12,
10
3,
0
72
3
HEVC
40
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
16
2
778
3
coef_probs_8x8
[1] [1] [1] [4]
[0..2]
6, 77,
123
6,
77,
12
3
0
72
6
781
3
coef_probs_8x8
[1] [1] [1] [5]
[0..2]
2, 53,
84
2,
53,
84
0
72
9
784
3
coef_probs_8x8
[1] [1] [2] [0]
[0..2]
75,
183,
239
75,
18
3,
23
9
0
73
2
787
3
coef_probs_8x8
[1] [1] [2] [1]
[0..2]
30,
155,
221
30,
15
5,
22
1
0
73
5
790
3
coef_probs_8x8
[1] [1] [2] [2]
[0..2]
3, 106,
171
3,
10
6,
17
1
0
73
8
793
3
coef_probs_8x8
[1] [1] [2] [3]
1, 74,
128
1,
74,
0
74
1
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
41
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0..2]
12
8
796
3
coef_probs_8x8
[1] [1] [2] [4]
[0..2]
1, 44,
76
1,
44,
76
0
74
4
799
3
coef_probs_8x8
[1] [1] [2] [5]
[0..2]
1, 17,
28
1,
17,
28
0
74
7
802
3
coef_probs_8x8
[1] [1] [3] [0]
[0..2]
73,
185,
240
73,
18
5,
24
0
0
75
0
805
3
coef_probs_8x8
[1] [1] [3] [1]
[0..2]
27,
159,
222
27,
15
9,
22
2
0
75
3
808
3
coef_probs_8x8
[1] [1] [3] [2]
[0..2]
2, 107,
172
2,
10
7,
17
2
0
75
6
811
3
coef_probs_8x8
[1] [1] [3] [3]
[0..2]
1, 75,
127
1,
75,
12
0
75
9
HEVC
42
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
7
814
3
coef_probs_8x8
[1] [1] [3] [4]
[0..2]
1, 42,
73
1,
42,
73
0
76
2
817
3
coef_probs_8x8
[1] [1] [3] [5]
[0..2]
1, 17,
29
1,
17,
29
0
76
5
820
3
coef_probs_8x8
[1] [1] [4] [0]
[0..2]
62,
190,
238
62,
19
0,
23
8
0
76
8
823
3
coef_probs_8x8
[1] [1] [4] [1]
[0..2]
21,
159,
222
21,
15
9,
22
2
0
77
1
826
3
coef_probs_8x8
[1] [1] [4] [2]
[0..2]
2, 107,
172
2,
10
7,
17
2
0
77
4
829
3
coef_probs_8x8
[1] [1] [4] [3]
[0..2]
1, 72,
122
1,
72,
12
2
0
77
7
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
43
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
832
3
coef_probs_8x8
[1] [1] [4] [4]
[0..2]
1, 40,
71
1,
40,
71
0
78
0
835
3
coef_probs_8x8
[1] [1] [4] [5]
[0..2]
1, 18,
32
1,
18,
32
0
78
3
838
3
coef_probs_8x8
[1] [1] [5] [0]
[0..2]
61,
199,
240
61,
19
9,
24
0
0
78
6
841
3
coef_probs_8x8
[1] [1] [5] [1]
[0..2]
27,
161,
226
27,
16
1,
22
6
0
78
9
844
3
coef_probs_8x8
[1] [1] [5] [2]
[0..2]
4, 113,
180
4,
11
3,
18
0
0
79
2
847
3
coef_probs_8x8
[1] [1] [5] [3]
[0..2]
1, 76,
129
1,
76,
12
9
0
79
5
850
3
coef_probs_8x8
1, 46,
1,
0
79
HEVC
44
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[1] [1] [5] [4]
[0..2]
80
46,
80
8
853
3
coef_probs_8x8
[1] [1] [5] [5]
[0..2]
1, 23,
41
1,
23,
41
0
80
1
856
3
coef_probs_16x1
6
[0] [0] [0] [0]
[0..2]
7, 27,
153
7,
27,
15
3
0
80
4
107
0-
287
859
3
coef_probs_16x1
6
[0] [0] [0] [1]
[0..2]
5, 30,
95
5,
30,
95
0
80
7
862
3
coef_probs_16x1
6
[0] [0] [0] [2]
[0..2]
1, 16,
30
1,
16,
30
0
81
0
865
3
coef_probs_16x1
6
[0] [0] [1] [0]
[0..2]
50, 75,
127
50,
75,
12
7
0
81
3
868
3
coef_probs_16x1
6
[0] [0] [1] [1]
[0..2]
57, 75,
124
57,
75,
12
4
0
81
6
871
3
coef_probs_16x1
27, 67,
27,
0
81
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
45
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
6
[0] [0] [1] [2]
[0..2]
108
67,
10
8
9
874
3
coef_probs_16x1
6
[0] [0] [1] [3]
[0..2]
10, 54,
86
10,
54,
86
0
82
2
877
3
coef_probs_16x1
6
[0] [0] [1] [4]
[0..2]
1, 33,
52
1,
33,
52
0
82
5
880
3
coef_probs_16x1
6
[0] [0] [1] [5]
[0..2]
1, 12,
18
1,
12,
18
0
82
8
883
3
coef_probs_16x1
6
[0] [0] [2] [0]
[0..2]
43,
125,
151
43,
12
5,
15
1
0
83
1
886
3
coef_probs_16x1
6
[0] [0] [2] [1]
[0..2]
26,
108,
148
26,
10
8,
14
8
0
83
4
889
3
coef_probs_16x1
7, 83,
7,
0
83
HEVC
46
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
6
[0] [0] [2] [2]
[0..2]
122
83,
12
2
7
892
3
coef_probs_16x1
6
[0] [0] [2] [3]
[0..2]
2, 59,
89
2,
59,
89
0
84
0
895
3
coef_probs_16x1
6
[0] [0] [2] [4]
[0..2]
1, 38,
60
1,
38,
60
0
84
3
898
3
coef_probs_16x1
6
[0] [0] [2] [5]
[0..2]
1, 17,
27
1,
17,
27
0
84
6
901
3
coef_probs_16x1
6
[0] [0] [3] [0]
[0..2]
23,
144,
163
23,
14
4,
16
3
0
84
9
904
3
coef_probs_16x1
6
[0] [0] [3] [1]
[0..2]
13,
112,
154
13,
11
2,
15
4
0
85
2
907
3
coef_probs_16x1
2, 75,
2,
0
85
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
47
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
6
[0] [0] [3] [2]
[0..2]
117
75,
11
7
5
910
3
coef_probs_16x1
6
[0] [0] [3] [3]
[0..2]
1, 50,
81
1,
50,
81
0
85
8
913
3
coef_probs_16x1
6
[0] [0] [3] [4]
[0..2]
1, 31,
51
1,
31,
51
0
86
1
916
3
coef_probs_16x1
6
[0] [0] [3] [5]
[0..2]
1, 14,
23
1,
14,
23
0
86
4
919
3
coef_probs_16x1
6
[0] [0] [4] [0]
[0..2]
18,
162,
185
18,
16
2,
18
5
0
86
7
922
3
coef_probs_16x1
6
[0] [0] [4] [1]
[0..2]
6, 123,
171
6,
12
3,
17
1
0
87
0
925
3
coef_probs_16x1
1, 78,
1,
0
87
HEVC
48
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
6
[0] [0] [4] [2]
[0..2]
125
78,
12
5
3
928
3
coef_probs_16x1
6
[0] [0] [4] [3]
[0..2]
1, 51,
86
1,
51,
86
0
87
6
931
3
coef_probs_16x1
6
[0] [0] [4] [4]
[0..2]
1, 31,
54
1,
31,
54
0
87
9
934
3
coef_probs_16x1
6
[0] [0] [4] [5]
[0..2]
1, 14,
23
1,
14,
23
0
88
2
937
3
coef_probs_16x1
6
[0] [0] [5] [0]
[0..2]
15,
199,
227
15,
19
9,
22
7
0
88
5
940
3
coef_probs_16x1
6
[0] [0] [5] [1]
[0..2]
3, 150,
204
3,
15
0,
20
4
0
88
8
943
3
coef_probs_16x1
1, 91,
1,
0
89
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
49
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
6
[0] [0] [5] [2]
[0..2]
146
91,
14
6
1
946
3
coef_probs_16x1
6
[0] [0] [5] [3]
[0..2]
1, 55,
95
1,
55,
95
0
89
4
949
3
coef_probs_16x1
6
[0] [0] [5] [4]
[0..2]
1, 30,
53
1,
30,
53
0
89
7
952
3
coef_probs_16x1
6
[0] [0] [5] [5]
[0..2]
1, 11,
20
1,
11,
20
0
90
0
955
3
coef_probs_16x1
6
[0] [1] [0] [0]
[0..2]
19, 55,
240
19,
55,
24
0
0
90
3
958
3
coef_probs_16x1
6
[0] [1] [0] [1]
[0..2]
19, 59,
196
19,
59,
19
6
0
90
6
961
3
coef_probs_16x1
6
[0] [1] [0] [2]
3, 52,
105
3,
52,
10
0
90
9
HEVC
50
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0..2]
5
964
3
coef_probs_16x1
6
[0] [1] [1] [0]
[0..2]
41,
166,
207
41,
16
6,
20
7
0
91
2
967
3
coef_probs_16x1
6
[0] [1] [1] [1]
[0..2]
104,
153,
199
10
4,
15
3,
19
9
0
91
5
970
3
coef_probs_16x1
6
[0] [1] [1] [2]
[0..2]
31,
123,
181
31,
12
3,
18
1
0
91
8
973
3
coef_probs_16x1
6
[0] [1] [1] [3]
[0..2]
14,
101,
152
14,
10
1,
15
2
0
92
1
976
3
coef_probs_16x1
6
[0] [1] [1] [4]
[0..2]
5, 72,
106
5,
72,
10
6
0
92
4
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
51
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
979
3
coef_probs_16x1
6
[0] [1] [1] [5]
[0..2]
1, 36,
52
1,
36,
52
0
92
7
982
3
coef_probs_16x1
6
[0] [1] [2] [0]
[0..2]
35,
176,
211
35,
17
6,
21
1
0
93
0
985
3
coef_probs_16x1
6
[0] [1] [2] [1]
[0..2]
12,
131,
190
12,
13
1,
19
0
0
93
3
988
3
coef_probs_16x1
6
[0] [1] [2] [2]
[0..2]
2, 88,
144
2,
88,
14
4
0
93
6
991
3
coef_probs_16x1
6
[0] [1] [2] [3]
[0..2]
1, 60,
101
1,
60,
10
1
0
93
9
994
3
coef_probs_16x1
6
[0] [1] [2] [4]
[0..2]
1, 36,
60
1,
36,
60
0
94
2
HEVC
52
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
997
3
coef_probs_16x1
6
[0] [1] [2] [5]
[0..2]
1, 16,
28
1,
16,
28
0
94
5
100
0
3
coef_probs_16x1
6
[0] [1] [3] [0]
[0..2]
28,
183,
213
28,
18
3,
21
3
0
94
8
100
3
3
coef_probs_16x1
6
[0] [1] [3] [1]
[0..2]
8, 134,
191
8,
13
4,
19
1
0
95
1
100
6
3
coef_probs_16x1
6
[0] [1] [3] [2]
[0..2]
1, 86,
142
1,
86,
14
2
0
95
4
100
9
3
coef_probs_16x1
6
[0] [1] [3] [3]
[0..2]
1, 56,
96
1,
56,
96
0
95
7
101
2
3
coef_probs_16x1
6
[0] [1] [3] [4]
[0..2]
1, 30,
53
1,
30,
53
0
96
0
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
53
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
101
5
3
coef_probs_16x1
6
[0] [1] [3] [5]
[0..2]
1, 12,
20
1,
12,
20
0
96
3
101
8
3
coef_probs_16x1
6
[0] [1] [4] [0]
[0..2]
20,
190,
215
20,
19
0,
21
5
0
96
6
102
1
3
coef_probs_16x1
6
[0] [1] [4] [1]
[0..2]
4, 135,
192
4,
13
5,
19
2
0
96
9
102
4
3
coef_probs_16x1
6
[0] [1] [4] [2]
[0..2]
1, 84,
139
1,
84,
13
9
0
97
2
102
7
3
coef_probs_16x1
6
[0] [1] [4] [3]
[0..2]
1, 53,
91
1,
53,
91
0
97
5
103
0
3
coef_probs_16x1
6
[0] [1] [4] [4]
[0..2]
1, 28,
49
1,
28,
49
0
97
8
HEVC
54
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
103
3
3
coef_probs_16x1
6
[0] [1] [4] [5]
[0..2]
1, 11,
20
1,
11,
20
0
98
1
103
6
3
coef_probs_16x1
6
[0] [1] [5] [0]
[0..2]
13,
196,
216
13,
19
6,
21
6
0
98
4
103
9
3
coef_probs_16x1
6
[0] [1] [5] [1]
[0..2]
2, 137,
192
2,
13
7,
19
2
0
98
7
104
2
3
coef_probs_16x1
6
[0] [1] [5] [2]
[0..2]
1, 86,
143
1,
86,
14
3
0
99
0
104
5
3
coef_probs_16x1
6
[0] [1] [5] [3]
[0..2]
1, 57,
99
1,
57,
99
0
99
3
104
8
3
coef_probs_16x1
6
[0] [1] [5] [4]
[0..2]
1, 32,
56
1,
32,
56
0
99
6
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
55
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
105
1
3
coef_probs_16x1
6
[0] [1] [5] [5]
[0..2]
1, 13,
24
1,
13,
24
0
99
9
105
4
3
coef_probs_16x1
6
[1] [0] [0] [0]
[0..2]
211,
29, 217
21
1,
29,
21
7
0
10
02
0-287
105
7
3
coef_probs_16x1
6
[1] [0] [0] [1]
[0..2]
96, 47,
156
96,
47,
15
6
0
10
05
106
0
3
coef_probs_16x1
6
[1] [0] [0] [2]
[0..2]
22, 43,
87
22,
43,
87
0
10
08
106
3
3
coef_probs_16x1
6
[1] [0] [1] [0]
[0..2]
78,
120,
193
78,
12
0,
19
3
0
10
11
106
6
3
coef_probs_16x1
6
[1] [0] [1] [1]
[0..2]
111,
116,
186
11
1,
11
6,
18
0
10
14
HEVC
56
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
6
106
9
3
coef_probs_16x1
6
[1] [0] [1] [2]
[0..2]
46,
102,
164
46,
10
2,
16
4
0
10
17
107
2
3
coef_probs_16x1
6
[1] [0] [1] [3]
[0..2]
15, 80,
128
15,
80,
12
8
0
10
20
107
5
3
coef_probs_16x1
6
[1] [0] [1] [4]
[0..2]
2, 49,
76
2,
49,
76
0
10
23
107
8
3
coef_probs_16x1
6
[1] [0] [1] [5]
[0..2]
1, 18,
28
1,
18,
28
0
10
26
108
1
3
coef_probs_16x1
6
[1] [0] [2] [0]
[0..2]
71,
161,
203
71,
16
1,
20
3
0
10
29
108
4
3
coef_probs_16x1
6
[1] [0] [2] [1]
42,
132,
192
42,
13
2,
0
10
32
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
57
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0..2]
19
2
108
7
3
coef_probs_16x1
6
[1] [0] [2] [2]
[0..2]
10, 98,
150
10,
98,
15
0
0
10
35
109
0
3
coef_probs_16x1
6
[1] [0] [2] [3]
[0..2]
3, 69,
109
3,
69,
10
9
0
10
38
109
3
3
coef_probs_16x1
6
[1] [0] [2] [4]
[0..2]
1, 44,
70
1,
44,
70
0
10
41
109
6
3
coef_probs_16x1
6
[1] [0] [2] [5]
[0..2]
1, 18,
29
1,
18,
29
0
10
44
109
9
3
coef_probs_16x1
6
[1] [0] [3] [0]
[0..2]
57,
186,
211
57,
18
6,
21
1
0
10
47
110
2
3
coef_probs_16x1
6
[1] [0] [3] [1]
30,
140,
196
30,
14
0,
0
10
50
HEVC
58
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0..2]
19
6
110
5
3
coef_probs_16x1
6
[1] [0] [3] [2]
[0..2]
4, 93,
146
4,
93,
14
6
0
10
53
110
8
3
coef_probs_16x1
6
[1] [0] [3] [3]
[0..2]
1, 62,
102
1,
62,
10
2
0
10
56
111
1
3
coef_probs_16x1
6
[1] [0] [3] [4]
[0..2]
1, 38,
65
1,
38,
65
0
10
59
111
4
3
coef_probs_16x1
6
[1] [0] [3] [5]
[0..2]
1, 16,
27
1,
16,
27
0
10
62
111
7
3
coef_probs_16x1
6
[1] [0] [4] [0]
[0..2]
47,
199,
217
47,
19
9,
21
7
0
10
65
112
0
3
coef_probs_16x1
6
[1] [0] [4] [1]
14,
145,
196
14,
14
5,
0
10
68
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
59
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0..2]
19
6
112
3
3
coef_probs_16x1
6
[1] [0] [4] [2]
[0..2]
1, 88,
142
1,
88,
14
2
0
10
71
112
6
3
coef_probs_16x1
6
[1] [0] [4] [3]
[0..2]
1, 57,
98
1,
57,
98
0
10
74
112
9
3
coef_probs_16x1
6
[1] [0] [4] [4]
[0..2]
1, 36,
62
1,
36,
62
0
10
77
113
2
3
coef_probs_16x1
6
[1] [0] [4] [5]
[0..2]
1, 15,
26
1,
15,
26
0
10
80
113
5
3
coef_probs_16x1
6
[1] [0] [5] [0]
[0..2]
26,
219,
229
26,
21
9,
22
9
0
10
83
113
8
3
coef_probs_16x1
6
[1] [0] [5] [1]
5, 155,
207
5,
15
5,
0
10
86
HEVC
60
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0..2]
20
7
114
1
3
coef_probs_16x1
6
[1] [0] [5] [2]
[0..2]
1, 94,
151
1,
94,
15
1
0
10
89
114
4
3
coef_probs_16x1
6
[1] [0] [5] [3]
[0..2]
1, 60,
104
1,
60,
10
4
0
10
92
114
7
3
coef_probs_16x1
6
[1] [0] [5] [4]
[0..2]
1, 36,
62
1,
36,
62
0
10
95
115
0
3
coef_probs_16x1
6
[1] [0] [5] [5]
[0..2]
1, 16,
28
1,
16,
28
0
10
98
115
3
3
coef_probs_16x1
6
[1] [1] [0] [0]
[0..2]
233,
29, 248
23
3,
29,
24
8
0
11
01
115
6
3
coef_probs_16x1
6
[1] [1] [0] [1]
146,
47, 220
14
6,
47,
0
11
04
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
61
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0..2]
22
0
115
9
3
coef_probs_16x1
6
[1] [1] [0] [2]
[0..2]
43, 52,
140
43,
52,
14
0
0
11
07
116
2
3
coef_probs_16x1
6
[1] [1] [1] [0]
[0..2]
100,
163,
232
10
0,
16
3,
23
2
0
11
10
116
5
3
coef_probs_16x1
6
[1] [1] [1] [1]
[0..2]
179,
161,
222
17
9,
16
1,
22
2
0
11
13
116
8
3
coef_probs_16x1
6
[1] [1] [1] [2]
[0..2]
63,
142,
204
63,
14
2,
20
4
0
11
16
117
1
3
coef_probs_16x1
6
[1] [1] [1] [3]
[0..2]
37,
113,
174
37,
11
3,
17
0
11
19
HEVC
62
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
4
117
4
3
coef_probs_16x1
6
[1] [1] [1] [4]
[0..2]
26, 89,
137
26,
89,
13
7
0
11
22
117
7
3
coef_probs_16x1
6
[1] [1] [1] [5]
[0..2]
18, 68,
97
18,
68,
97
0
11
25
118
0
3
coef_probs_16x1
6
[1] [1] [2] [0]
[0..2]
85,
181,
230
85,
18
1,
23
0
0
11
28
118
3
3
coef_probs_16x1
6
[1] [1] [2] [1]
[0..2]
32,
146,
209
32,
14
6,
20
9
0
11
31
118
6
3
coef_probs_16x1
6
[1] [1] [2] [2]
[0..2]
7, 100,
164
7,
10
0,
16
4
0
11
34
118
9
3
coef_probs_16x1
6
3, 71,
121
3,
71,
0
11
37
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
63
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[1] [1] [2] [3]
[0..2]
12
1
119
2
3
coef_probs_16x1
6
[1] [1] [2] [4]
[0..2]
1, 45,
77
1,
45,
77
0
11
40
119
5
3
coef_probs_16x1
6
[1] [1] [2] [5]
[0..2]
1, 18,
30
1,
18,
30
0
11
43
119
8
3
coef_probs_16x1
6
[1] [1] [3] [0]
[0..2]
65,
187,
230
65,
18
7,
23
0
0
11
46
120
1
3
coef_probs_16x1
6
[1] [1] [3] [1]
[0..2]
20,
148,
207
20,
14
8,
20
7
0
11
49
120
4
3
coef_probs_16x1
6
[1] [1] [3] [2]
[0..2]
2, 97,
159
2,
97,
15
9
0
11
52
120
7
3
coef_probs_16x1
6
1, 68,
116
1,
68,
0
11
55
HEVC
64
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[1] [1] [3] [3]
[0..2]
11
6
121
0
3
coef_probs_16x1
6
[1] [1] [3] [4]
[0..2]
1, 40,
70
1,
40,
70
0
11
58
121
3
3
coef_probs_16x1
6
[1] [1] [3] [5]
[0..2]
1, 14,
29
1,
14,
29
0
11
61
121
6
3
coef_probs_16x1
6
[1] [1] [4] [0]
[0..2]
40,
194,
227
40,
19
4,
22
7
0
11
64
121
9
3
coef_probs_16x1
6
[1] [1] [4] [1]
[0..2]
8, 147,
204
8,
14
7,
20
4
0
11
67
122
2
3
coef_probs_16x1
6
[1] [1] [4] [2]
[0..2]
1, 94,
155
1,
94,
15
5
0
11
70
122
5
3
coef_probs_16x1
6
1, 65,
112
1,
65,
0
11
73
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
65
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[1] [1] [4] [3]
[0..2]
11
2
122
8
3
coef_probs_16x1
6
[1] [1] [4] [4]
[0..2]
1, 39,
66
1,
39,
66
0
11
76
123
1
3
coef_probs_16x1
6
[1] [1] [4] [5]
[0..2]
1, 14,
26
1,
14,
26
0
11
79
123
4
3
coef_probs_16x1
6
[1] [1] [5] [0]
[0..2]
16,
208,
228
16,
20
8,
22
8
0
11
82
123
7
3
coef_probs_16x1
6
[1] [1] [5] [1]
[0..2]
3, 151,
207
3,
15
1,
20
7
0
11
85
124
0
3
coef_probs_16x1
6
[1] [1] [5] [2]
[0..2]
1, 98,
160
1,
98,
16
0
0
11
88
124
3
3
coef_probs_16x1
6
1, 67,
117
1,
67,
0
11
91
HEVC
66
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[1] [1] [5] [3]
[0..2]
11
7
124
6
3
coef_probs_16x1
6
[1] [1] [5] [4]
[0..2]
1, 41,
74
1,
41,
74
0
11
94
124
9
3
coef_probs_16x1
6
[1] [1] [5] [5]
[0..2]
1, 17,
31
1,
17,
31
0
11
97
125
2
3
coef_probs_32x3
2
[0] [0] [0] [0]
[0..2]
17, 38,
140
17,
38,
14
0
0
12
00
156
.5
0-
287
125
5
3
coef_probs_32x3
2
[0] [0] [0] [1]
[0..2]
7, 34,
80
7,
34,
80
0
12
03
125
8
3
coef_probs_32x3
2
[0] [0] [0] [2]
[0..2]
1, 17,
29
1,
17,
29
0
12
06
126
1
3
coef_probs_32x3
2
[0] [0] [1] [0]
[0..2]
37, 75,
128
37,
75,
12
8
0
12
09
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
67
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
126
4
3
coef_probs_32x3
2
[0] [0] [1] [1]
[0..2]
41, 76,
128
41,
76,
12
8
0
12
12
126
7
3
coef_probs_32x3
2
[0] [0] [1] [2]
[0..2]
26, 66,
116
26,
66,
11
6
0
12
15
127
0
3
coef_probs_32x3
2
[0] [0] [1] [3]
[0..2]
12, 52,
94
12,
52,
94
0
12
18
127
3
3
coef_probs_32x3
2
[0] [0] [1] [4]
[0..2]
2, 32,
55
2,
32,
55
0
12
21
127
6
3
coef_probs_32x3
2
[0] [0] [1] [5]
[0..2]
1, 10,
16
1,
10,
16
0
12
24
127
9
3
coef_probs_32x3
2
[0] [0] [2] [0]
[0..2]
50,
127,
154
50,
12
7,
15
4
0
12
27
128
3
coef_probs_32x3
37,
37,
0
12
HEVC
68
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
2
2
[0] [0] [2] [1]
[0..2]
109,
152
10
9,
15
2
30
128
5
3
coef_probs_32x3
2
[0] [0] [2] [2]
[0..2]
16, 82,
121
16,
82,
12
1
0
12
33
128
8
3
coef_probs_32x3
2
[0] [0] [2] [3]
[0..2]
5, 59,
85
5,
59,
85
0
12
36
129
1
3
coef_probs_32x3
2
[0] [0] [2] [4]
[0..2]
1, 35,
54
1,
35,
54
0
12
39
129
4
3
coef_probs_32x3
2
[0] [0] [2] [5]
[0..2]
1, 13,
20
1,
13,
20
0
12
42
129
7
3
coef_probs_32x3
2
[0] [0] [3] [0]
[0..2]
40,
142,
167
40,
14
2,
16
7
0
12
45
130
3
coef_probs_32x3
17,
17,
0
12
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
69
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
0
2
[0] [0] [3] [1]
[0..2]
110,
157
11
0,
15
7
48
130
3
3
coef_probs_32x3
2
[0] [0] [3] [2]
[0..2]
2, 71,
112
2,
71,
11
2
0
12
51
130
6
3
coef_probs_32x3
2
[0] [0] [3] [3]
[0..2]
1, 44,
72
1,
44,
72
0
12
54
130
9
3
coef_probs_32x3
2
[0] [0] [3] [4]
[0..2]
1, 27,
45
1,
27,
45
0
12
57
131
2
3
coef_probs_32x3
2
[0] [0] [3] [5]
[0..2]
1, 11,
17
1,
11,
17
0
12
60
131
5
3
coef_probs_32x3
2
[0] [0] [4] [0]
[0..2]
30,
175,
188
30,
17
5,
18
8
0
12
63
131
3
coef_probs_32x3
9, 124,
9,
0
12
HEVC
70
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
8
2
[0] [0] [4] [1]
[0..2]
169
12
4,
16
9
66
132
1
3
coef_probs_32x3
2
[0] [0] [4] [2]
[0..2]
1, 74,
116
1,
74,
11
6
0
12
69
132
4
3
coef_probs_32x3
2
[0] [0] [4] [3]
[0..2]
1, 48,
78
1,
48,
78
0
12
72
132
7
3
coef_probs_32x3
2
[0] [0] [4] [4]
[0..2]
1, 30,
49
1,
30,
49
0
12
75
133
0
3
coef_probs_32x3
2
[0] [0] [4] [5]
[0..2]
1, 11,
18
1,
11,
18
0
12
78
133
3
3
coef_probs_32x3
2
[0] [0] [5] [0]
[0..2]
10,
222,
223
10,
22
2,
22
3
0
12
81
133
3
coef_probs_32x3
2, 150,
2,
0
12
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
71
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
6
2
[0] [0] [5] [1]
[0..2]
194
15
0,
19
4
84
133
9
3
coef_probs_32x3
2
[0] [0] [5] [2]
[0..2]
1, 83,
128
1,
83,
12
8
0
12
87
134
2
3
coef_probs_32x3
2
[0] [0] [5] [3]
[0..2]
1, 48,
79
1,
48,
79
0
12
90
134
5
3
coef_probs_32x3
2
[0] [0] [5] [4]
[0..2]
1, 27,
45
1,
27,
45
0
12
93
134
8
3
coef_probs_32x3
2
[0] [0] [5] [5]
[0..2]
1, 11,
17
1,
11,
17
0
12
96
135
1
3
coef_probs_32x3
2
[0] [1] [0] [0]
[0..2]
36, 41,
235
36,
41,
23
5
0
12
99
135
4
3
coef_probs_32x3
2
29, 36,
193
29,
36,
0
13
02
HEVC
72
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0] [1] [0] [1]
[0..2]
19
3
135
7
3
coef_probs_32x3
2
[0] [1] [0] [2]
[0..2]
10, 27,
111
10,
27,
11
1
0
13
05
136
0
3
coef_probs_32x3
2
[0] [1] [1] [0]
[0..2]
85,
165,
222
85,
16
5,
22
2
0
13
08
136
3
3
coef_probs_32x3
2
[0] [1] [1] [1]
[0..2]
177,
162,
215
17
7,
16
2,
21
5
0
13
11
136
6
3
coef_probs_32x3
2
[0] [1] [1] [2]
[0..2]
110,
135,
195
11
0,
13
5,
19
5
0
13
14
136
9
3
coef_probs_32x3
2
[0] [1] [1] [3]
[0..2]
57,
113,
168
57,
11
3,
16
0
13
17
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
73
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
8
137
2
3
coef_probs_32x3
2
[0] [1] [1] [4]
[0..2]
23, 83,
120
23,
83,
12
0
0
13
20
137
5
3
coef_probs_32x3
2
[0] [1] [1] [5]
[0..2]
10, 49,
61
10,
49,
61
0
13
23
137
8
3
coef_probs_32x3
2
[0] [1] [2] [0]
[0..2]
85,
190,
223
85,
19
0,
22
3
0
13
26
138
1
3
coef_probs_32x3
2
[0] [1] [2] [1]
[0..2]
36,
139,
200
36,
13
9,
20
0
0
13
29
138
4
3
coef_probs_32x3
2
[0] [1] [2] [2]
[0..2]
5, 90,
146
5,
90,
14
6
0
13
32
138
7
3
coef_probs_32x3
2
[0] [1] [2] [3]
1, 60,
103
1,
60,
10
0
13
35
HEVC
74
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0..2]
3
139
0
3
coef_probs_32x3
2
[0] [1] [2] [4]
[0..2]
1, 38,
65
1,
38,
65
0
13
38
139
3
3
coef_probs_32x3
2
[0] [1] [2] [5]
[0..2]
1, 18,
30
1,
18,
30
0
13
41
139
6
3
coef_probs_32x3
2
[0] [1] [3] [0]
[0..2]
72,
202,
223
72,
20
2,
22
3
0
13
44
139
9
3
coef_probs_32x3
2
[0] [1] [3] [1]
[0..2]
23,
141,
199
23,
14
1,
19
9
0
13
47
140
2
3
coef_probs_32x3
2
[0] [1] [3] [2]
[0..2]
2, 86,
140
2,
86,
14
0
0
13
50
140
5
3
coef_probs_32x3
2
[0] [1] [3] [3]
1, 56,
97
1,
56,
97
0
13
53
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
75
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0..2]
140
8
3
coef_probs_32x3
2
[0] [1] [3] [4]
[0..2]
1, 36,
61
1,
36,
61
0
13
56
141
1
3
coef_probs_32x3
2
[0] [1] [3] [5]
[0..2]
1, 16,
27
1,
16,
27
0
13
59
141
4
3
coef_probs_32x3
2
[0] [1] [4] [0]
[0..2]
55,
218,
225
55,
21
8,
22
5
0
13
62
141
7
3
coef_probs_32x3
2
[0] [1] [4] [1]
[0..2]
13,
145,
200
13,
14
5,
20
0
0
13
65
142
0
3
coef_probs_32x3
2
[0] [1] [4] [2]
[0..2]
1, 86,
141
1,
86,
14
1
0
13
68
142
3
3
coef_probs_32x3
2
[0] [1] [4] [3]
1, 57,
99
1,
57,
99
0
13
71
HEVC
76
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0..2]
142
6
3
coef_probs_32x3
2
[0] [1] [4] [4]
[0..2]
1, 35,
61
1,
35,
61
0
13
74
142
9
3
coef_probs_32x3
2
[0] [1] [4] [5]
[0..2]
1, 13,
22
1,
13,
22
0
13
77
143
2
3
coef_probs_32x3
2
[0] [1] [5] [0]
[0..2]
15,
235,
212
15,
23
5,
21
2
0
13
80
143
5
3
coef_probs_32x3
2
[0] [1] [5] [1]
[0..2]
1, 132,
184
1,
13
2,
18
4
0
13
83
143
8
3
coef_probs_32x3
2
[0] [1] [5] [2]
[0..2]
1, 84,
139
1,
84,
13
9
0
13
86
144
1
3
coef_probs_32x3
2
[0] [1] [5] [3]
1, 57,
97
1,
57,
97
0
13
89
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
77
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0..2]
144
4
3
coef_probs_32x3
2
[0] [1] [5] [4]
[0..2]
1, 34,
56
1,
34,
56
0
13
92
144
7
3
coef_probs_32x3
2
[0] [1] [5] [5]
[0..2]
1, 14,
23
1,
14,
23
0
13
95
145
0
3
coef_probs_32x3
2
[1] [0] [0] [0]
[0..2]
181,
21, 201
18
1,
21,
20
1
0
13
98
0-287
145
3
3
coef_probs_32x3
2
[1] [0] [0] [1]
[0..2]
61, 37,
123
61,
37,
12
3
0
14
01
145
6
3
coef_probs_32x3
2
[1] [0] [0] [2]
[0..2]
10, 38,
71
10,
38,
71
0
14
04
145
9
3
coef_probs_32x3
2
[1] [0] [1] [0]
[0..2]
47,
106,
172
47,
10
6,
17
0
14
07
HEVC
78
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
2
146
2
3
coef_probs_32x3
2
[1] [0] [1] [1]
[0..2]
95,
104,
173
95,
10
4,
17
3
0
14
10
146
5
3
coef_probs_32x3
2
[1] [0] [1] [2]
[0..2]
42, 93,
159
42,
93,
15
9
0
14
13
146
8
3
coef_probs_32x3
2
[1] [0] [1] [3]
[0..2]
18, 77,
131
18,
77,
13
1
0
14
16
147
1
3
coef_probs_32x3
2
[1] [0] [1] [4]
[0..2]
4, 50,
81
4,
50,
81
0
14
19
147
4
3
coef_probs_32x3
2
[1] [0] [1] [5]
[0..2]
1, 17,
23
1,
17,
23
0
14
22
147
7
3
coef_probs_32x3
2
[1] [0] [2] [0]
[0..2]
62,
147,
199
62,
14
7,
19
0
14
25
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
79
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
9
148
0
3
coef_probs_32x3
2
[1] [0] [2] [1]
[0..2]
44,
130,
189
44,
13
0,
18
9
0
14
28
148
3
3
coef_probs_32x3
2
[1] [0] [2] [2]
[0..2]
28,
102,
154
28,
10
2,
15
4
0
14
31
148
6
3
coef_probs_32x3
2
[1] [0] [2] [3]
[0..2]
18, 75,
115
18,
75,
11
5
0
14
34
148
9
3
coef_probs_32x3
2
[1] [0] [2] [4]
[0..2]
2, 44,
65
2,
44,
65
0
14
37
149
2
3
coef_probs_32x3
2
[1] [0] [2] [5]
[0..2]
1, 12,
19
1,
12,
19
0
14
40
149
5
3
coef_probs_32x3
2
[1] [0] [3] [0]
55,
153,
210
55,
15
3,
0
14
43
HEVC
80
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0..2]
21
0
149
8
3
coef_probs_32x3
2
[1] [0] [3] [1]
[0..2]
24,
130,
194
24,
13
0,
19
4
0
14
46
150
1
3
coef_probs_32x3
2
[1] [0] [3] [2]
[0..2]
3, 93,
146
3,
93,
14
6
0
14
49
150
4
3
coef_probs_32x3
2
[1] [0] [3] [3]
[0..2]
1, 61,
97
1,
61,
97
0
14
52
150
7
3
coef_probs_32x3
2
[1] [0] [3] [4]
[0..2]
1, 31,
50
1,
31,
50
0
14
55
151
0
3
coef_probs_32x3
2
[1] [0] [3] [5]
[0..2]
1, 10,
16
1,
10,
16
0
14
58
151
3
3
coef_probs_32x3
2
[1] [0] [4] [0]
49,
186,
223
49,
18
6,
0
14
61
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
81
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0..2]
22
3
151
6
3
coef_probs_32x3
2
[1] [0] [4] [1]
[0..2]
17,
148,
204
17,
14
8,
20
4
0
14
64
151
9
3
coef_probs_32x3
2
[1] [0] [4] [2]
[0..2]
1, 96,
142
1,
96,
14
2
0
14
67
152
2
3
coef_probs_32x3
2
[1] [0] [4] [3]
[0..2]
1, 53,
83
1,
53,
83
0
14
70
152
5
3
coef_probs_32x3
2
[1] [0] [4] [4]
[0..2]
1, 26,
44
1,
26,
44
0
14
73
152
8
3
coef_probs_32x3
2
[1] [0] [4] [5]
[0..2]
1, 11,
17
1,
11,
17
0
14
76
153
1
3
coef_probs_32x3
2
[1] [0] [5] [0]
13,
217,
212
13,
21
7,
0
14
79
HEVC
82
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0..2]
21
2
153
4
3
coef_probs_32x3
2
[1] [0] [5] [1]
[0..2]
2, 136,
180
2,
13
6,
18
0
0
14
82
153
7
3
coef_probs_32x3
2
[1] [0] [5] [2]
[0..2]
1, 78,
124
1,
78,
12
4
0
14
85
154
0
3
coef_probs_32x3
2
[1] [0] [5] [3]
[0..2]
1, 50,
83
1,
50,
83
0
14
88
154
3
3
coef_probs_32x3
2
[1] [0] [5] [4]
[0..2]
1, 29,
49
1,
29,
49
0
14
91
154
6
3
coef_probs_32x3
2
[1] [0] [5] [5]
[0..2]
1, 14,
23
1,
14,
23
0
14
94
154
9
3
coef_probs_32x3
2
[1] [1] [0] [0]
197,
13, 247
19
7,
13,
0
14
97
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
83
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0..2]
24
7
155
2
3
coef_probs_32x3
2
[1] [1] [0] [1]
[0..2]
82, 17,
222
82,
17,
22
2
0
15
00
155
5
3
coef_probs_32x3
2
[1] [1] [0] [2]
[0..2]
25, 17,
162
25,
17,
16
2
0
15
03
155
8
3
coef_probs_32x3
2
[1] [1] [1] [0]
[0..2]
126,
186,
247
12
6,
18
6,
24
7
0
15
06
156
1
3
coef_probs_32x3
2
[1] [1] [1] [1]
[0..2]
234,
191,
243
23
4,
19
1,
24
3
0
15
09
156
4
3
coef_probs_32x3
2
[1] [1] [1] [2]
[0..2]
176,
177,
234
17
6,
17
7,
23
0
15
12
HEVC
84
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
4
156
7
3
coef_probs_32x3
2
[1] [1] [1] [3]
[0..2]
104,
158,
220
10
4,
15
8,
22
0
0
15
15
157
0
3
coef_probs_32x3
2
[1] [1] [1] [4]
[0..2]
66,
128,
186
66,
12
8,
18
6
0
15
18
157
3
3
coef_probs_32x3
2
[1] [1] [1] [5]
[0..2]
55, 90,
137
55,
90,
13
7
0
15
21
157
6
3
coef_probs_32x3
2
[1] [1] [2] [0]
[0..2]
111,
197,
242
11
1,
19
7,
24
2
0
15
24
157
9
3
coef_probs_32x3
2
[1] [1] [2] [1]
[0..2]
46,
158,
219
46,
15
8,
21
9
0
15
27
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
85
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
158
2
3
coef_probs_32x3
2
[1] [1] [2] [2]
[0..2]
9, 104,
171
9,
10
4,
17
1
0
15
30
158
5
3
coef_probs_32x3
2
[1] [1] [2] [3]
[0..2]
2, 65,
125
2,
65,
12
5
0
15
33
158
8
3
coef_probs_32x3
2
[1] [1] [2] [4]
[0..2]
1, 44,
80
1,
44,
80
0
15
36
159
1
3
coef_probs_32x3
2
[1] [1] [2] [5]
[0..2]
1, 17,
91
1,
17,
91
0
15
39
159
4
3
coef_probs_32x3
2
[1] [1] [3] [0]
[0..2]
104,
208,
245
10
4,
20
8,
24
5
0
15
42
159
7
3
coef_probs_32x3
2
[1] [1] [3] [1]
[0..2]
39,
168,
224
39,
16
8,
22
0
15
45
HEVC
86
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
4
160
0
3
coef_probs_32x3
2
[1] [1] [3] [2]
[0..2]
3, 109,
162
3,
10
9,
16
2
0
15
48
160
3
3
coef_probs_32x3
2
[1] [1] [3] [3]
[0..2]
1, 79,
124
1,
79,
12
4
0
15
51
160
6
3
coef_probs_32x3
2
[1] [1] [3] [4]
[0..2]
1, 50,
102
1,
50,
10
2
0
15
54
160
9
3
coef_probs_32x3
2
[1] [1] [3] [5]
[0..2]
1, 43,
102
1,
43,
10
2
0
15
57
161
2
3
coef_probs_32x3
2
[1] [1] [4] [0]
[0..2]
84,
220,
246
84,
22
0,
24
6
0
15
60
161
5
3
coef_probs_32x3
2
[1] [1] [4] [1]
31,
177,
231
31,
17
7,
0
15
63
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
87
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[0..2]
23
1
161
8
3
coef_probs_32x3
2
[1] [1] [4] [2]
[0..2]
2, 115,
180
2,
11
5,
18
0
0
15
66
162
1
3
coef_probs_32x3
2
[1] [1] [4] [3]
[0..2]
1, 79,
134
1,
79,
13
4
0
15
69
162
4
3
coef_probs_32x3
2
[1] [1] [4] [4]
[0..2]
1, 55,
77
1,
55,
77
0
15
72
162
7
3
coef_probs_32x3
2
[1] [1] [4] [5]
[0..2]
1, 60,
79
1,
60,
79
0
15
75
163
0
3
coef_probs_32x3
2
[1] [1] [5] [0]
[0..2]
43,
243,
240
43,
24
3,
24
0
0
15
78
163
3
3
coef_probs_32x3
2
8, 180,
217
8,
18
0
15
81
HEVC
88
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
[1] [1] [5] [1]
[0..2]
0,
21
7
163
6
3
coef_probs_32x3
2
[1] [1] [5] [2]
[0..2]
1, 115,
166
1,
11
5,
16
6
0
15
84
163
9
3
coef_probs_32x3
2
[1] [1] [5] [3]
[0..2]
1, 84,
121
1,
84,
12
1
0
15
87
164
2
3
coef_probs_32x3
2
[1] [1] [5] [4]
[0..2]
1, 51,
67
1,
51,
67
0
15
90
164
5
3
coef_probs_32x3
2
[1] [1] [5] [5]
[0..2]
1, 16, 6
1,
16,
6
0
15
93
164
8
16
DUMMY
0, 0, 0,
0, 0, 0,
0, 0, 0,
0, 0, 0,
0, 0, 0,
0
0,
0,
0,
0,
0,
0,
0,
16
15
96
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
89
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
0,
0,
0,
0,
0,
0,
0,
0,
0
CL
aligned
166
4
3
mbskip_probs
[0..2]
192,
128, 64
19
2,
12
8,
64
0
15
96
12
208
MODE COUNTERS
(Others)
18-23
166
7
3
inter_mode_prob
s
[0] [0..2]
0, 0, 0
2,
17
3,
34
0
15
99
15
24-51
167
0
3
inter_mode_prob
s
[1] [0..2]
0, 0, 0
7,
14
5,
85
0
16
02
18
167
3
3
inter_mode_prob
s
[2] [0..2]
0, 0, 0
7,
16
6,
63
0
16
05
21
167
3
inter_mode_prob
0, 0, 0
7,
0
16
24
HEVC
90
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
6
s
[3] [0..2]
94,
66
08
167
9
3
inter_mode_prob
s
[4] [0..2]
0, 0, 0
8,
64,
46
0
16
11
27
168
2
3
inter_mode_prob
s
[5] [0..2]
0, 0, 0
17,
81,
31
0
16
14
30
168
5
3
inter_mode_prob
s
[6] [0..2]
0, 0, 0
25,
29,
30
0
16
17
33
168
8
2
switchable_inter
p_probs
[0] [0..1]
0, 0
23
5,
16
2
0
16
20
36
52-63
169
0
2
switchable_inter
p_probs
[1] [0..1]
0, 0
36,
25
5
0
16
22
38
169
2
2
switchable_inter
p_probs
[2] [0..1]
0, 0
34,
3
0
16
24
40
169
4
2
switchable_inter
p_probs
[3] [0..1]
0, 0
14
9,
14
0
16
26
42
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
91
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
4
169
6
4
intra_inter_probs
[0..3]
0, 0, 0,
0
9,
10
2,
18
7,
22
5
0
16
28
44
64-71
170
0
5
comp_inter_prob
s
[0..4]
0, 0, 0,
0, 0
23
9,
18
3,
11
9,
96,
41
0
16
32
48
72-81
170
5
2
single_ref_probs
[0] [0..1]
0, 0
33,
16
0
16
37
53
82-
101
170
7
2
single_ref_probs
[1] [0..1]
0, 0
77,
74
0
16
39
55
170
9
2
single_ref_probs
[2] [0..1]
0, 0
14
2,
14
2
0
16
41
57
171
2
single_ref_probs
0, 0
17
0
16
59
HEVC
92
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
1
[3] [0..1]
2,
17
0
43
171
3
2
single_ref_probs
[4] [0..1]
0, 0
23
8,
24
7
0
16
45
61
171
5
5
comp_ref_probs
[0..4]
0, 0, 0,
0, 0
50,
12
6,
12
3,
22
1,
22
6
0
16
47
63
102-
111
172
0
9
y_mode_probs
[0] [0..8]
0, 0, 0,
0, 0, 0,
0, 0, 0
65,
32,
18,
14
4,
16
2,
19
4,
41,
51,
0
16
52
68
112-
151
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
93
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
98
172
9
9
y_mode_probs
[1] [0..8]
0, 0, 0,
0, 0, 0,
0, 0, 0
13
2,
68,
18,
16
5,
21
7,
19
6,
45,
40,
78
0
16
61
77
173
8
9
y_mode_probs
[2] [0..8]
0, 0, 0,
0, 0, 0,
0, 0, 0
17
3,
80,
19,
17
6,
24
0,
19
3,
64,
35,
46
0
16
70
86
HEVC
94
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
174
7
9
y_mode_probs
[3] [0..8]
0, 0, 0,
0, 0, 0,
0, 0, 0
22
1,
13
5,
38,
19
4,
24
8,
12
1,
96,
85,
29
0
16
79
95
175
6
3
partition_probs
[0] [0..2]
158,
97, 94
19
9,
12
2,
14
1
0
16
88
10
4
152-
215
175
9
3
partition_probs
[1] [0..2]
93, 24,
99
14
7,
63,
15
9
0
16
91
10
7
176
2
3
partition_probs
[2] [0..2]
85,
119, 44
14
8,
0
16
94
11
0
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
95
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
13
3,
11
8
176
5
3
partition_probs
[3] [0..2]
62, 59,
67
12
1,
10
4,
11
4
0
16
97
11
3
176
8
3
partition_probs
[4] [0..2]
149,
53, 53
17
4,
73,
87
0
17
00
11
6
177
1
3
partition_probs
[5] [0..2]
94, 20,
48
92,
41,
83
0
17
03
11
9
177
4
3
partition_probs
[6] [0..2]
83, 53,
24
82,
99,
50
0
17
06
12
2
177
7
3
partition_probs
[7] [0..2]
52, 18,
18
53,
39,
39
0
17
09
12
5
178
0
3
partition_probs
[8] [0..2]
150,
40, 39
17
7,
58,
0
17
12
12
8
HEVC
96
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
59
178
3
3
partition_probs
[9] [0..2]
78, 12,
26
68,
26,
63
0
17
15
13
1
178
6
3
partition_probs
[10] [0..2]
67, 33,
11
52,
79,
25
0
17
18
13
4
178
9
3
partition_probs
[11] [0..2]
24, 7, 5
17,
14,
12
0
17
21
13
7
179
2
3
partition_probs
[12] [0..2]
174,
35, 49
22
2,
34,
30
0
17
24
14
0
179
5
3
partition_probs
[13] [0..2]
68, 11,
27
72,
16,
44
0
17
27
14
3
179
8
3
partition_probs
[14] [0..2]
57, 15,
9
58,
32,
12
0
17
30
14
6
180
1
3
partition_probs
[15] [0..2]
12, 3, 3
10,
7,
6
0
17
33
14
9
180
4
3
mvc_joints
[3]
?,?,?
?,?,
?
0
17
36
15
2
MV COUNTERS
216-
219
180
1
mv_sign
0
12
0
17
15
220-
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
97
Alignm
ent
Ne
w
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#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
7
[0]
8
39
5
221
180
8
10
mv_classes
[0] [0..9]
0, 0, 0,
0, 0, 0,
0, 0, 0,
0
22
4,
14
4,
19
2,
16
8,
19
2,
17
6,
19
2,
19
8,
19
8,
24
5
0
17
40
15
6
222-
232
181
8
1
mv_class0
[0] [0..0]
0
21
6
0
17
50
16
6
233-
234
181
9
10
mv_bits
[0] [0..9]
0, 0, 0,
0, 0, 0,
0, 0, 0,
0
13
6,
14
0,
0
17
51
16
7
235-
254
HEVC
98
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
14
8,
16
0,
17
6,
19
2,
22
4,
23
4,
23
4,
24
0
182
9
1
mv_sign
[1]
0
12
8
0
17
61
17
7
255-
256
183
0
10
mv_classes
[1] [0..9]
0, 0, 0,
0, 0, 0,
0, 0, 0,
0
21
6,
12
8,
17
6,
16
0,
17
6,
0
17
62
17
8
257-
267
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
99
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
17
6,
19
2,
19
8,
19
8,
20
8
184
0
1
mv_class0
[1] [0..0]
0
20
8
0
17
72
18
8
268-
269
184
1
10
mv_bits
[1] [0..9]
0, 0, 0,
0, 0, 0,
0, 0, 0,
0
13
6,
14
0,
14
8,
16
0,
17
6,
19
2,
22
4,
23
4,
0
17
73
18
9
270-
289
HEVC
100
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
23
4,
24
0
185
1
3
mv_class0_fp
[0] [0] [0..2]
0, 0, 0
12
8,
12
8,
64
0
17
83
19
9
290-
297
185
4
3
mv_class0_fp
[0] [1] [0..2]
0, 0, 0
96,
11
2,
64
0
17
86
20
2
186
3
3
mv_fp
[0] [0..2]
0, 0, 0
64,
96,
64
0
17
89
20
5
298-
301
185
7
3
mv_class0_fp
[1] [0] [0..2]
0, 0, 0
12
8,
12
8,
64
0
17
92
20
8
302-
309
186
0
3
mv_class0_fp
[1] [1] [0..2]
0, 0, 0
96,
11
2,
64
0
17
95
21
1
186
3
mv_fp
0, 0, 0
64,
0
17
21
310-
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
101
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ent
Ne
w
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et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
6
[1] [0..2]
96,
64
98
4
313
186
9
2
mv_class0_hp
[0..1]
0, 0
16
0,
16
0
0
18
01
21
7
314-
315
187
1
2
mv_hp
[0..1]
0, 0
12
8,
12
8
0
18
03
21
9
316-
317
187
3
47
DUMMY
0, 0, 0,
0, 0, 0,
0, 0, 0,
0, 0, 0,
0, 0, 0,
0, 0, 0,
0, 0, 0,
0, 0, 0,
0, 0, 0,
0, 0, 0,
0, 0, 0,
0, 0, 0,
0, 0, 0,
0, 0, 0,
0, 0, 0,
0, 0
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
47
18
05
22
1
HEVC
102
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
103
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
0,
0
CL
aligned
192
0
9
uv_mode_probs
[0] [0..8]
144,
11, 54,
157,
195,
130,
46, 58,
108
12
0,
7,
76,
17
6,
20
8,
12
6,
28,
54,
10
3
0
18
05
22
1
240
MODE COUNTERS
(Others)
318-
417
192
9
9
uv_mode_probs
[1] [0..8]
118,
15,
123,
148,
131,
101,
44, 93,
131
48,
12,
15
4,
15
5,
13
9,
90,
34,
11
7,
0
18
14
23
0
HEVC
104
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
11
9
193
8
9
uv_mode_probs
[2] [0..8]
113,
12, 23,
188,
226,
142,
26, 32,
125
67,
6,
25,
20
4,
24
3,
15
8,
13,
21,
96
0
18
23
23
9
194
7
9
uv_mode_probs
[3] [0..8]
120,
11, 50,
123,
163,
135,
64, 77,
103
97,
5,
44,
13
1,
17
6,
13
9,
48,
68,
97
0
18
32
24
8
195
9
uv_mode_probs
113, 9,
83,
0
18
25
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
105
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
6
[4] [0..8]
36,
155,
111,
157,
32, 44,
161
5,
42,
15
6,
11
1,
15
2,
26,
49,
15
2
41
7
196
5
9
uv_mode_probs
[5] [0..8]
116, 9,
55,
176,
76, 96,
37, 61,
149
80,
5,
58,
17
8,
74,
83,
33,
62,
14
5
0
18
50
26
6
197
4
9
uv_mode_probs
[6] [0..8]
115, 9,
28,
141,
161,
167,
86,
5,
32,
15
4,
0
18
59
27
5
HEVC
106
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
21, 25,
193
19
2,
16
8,
14,
22,
16
3
198
3
9
uv_mode_probs
[7] [0..8]
120,
12, 32,
145,
195,
142,
32, 38,
86
85,
5,
32,
15
6,
21
6,
14
8,
19,
29,
73
0
18
68
28
4
199
2
9
uv_mode_probs
[8] [0..8]
116,
12, 64,
120,
140,
125,
49,
115,
121
77,
7,
64,
11
6,
13
2,
12
0
18
77
29
3
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
107
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
2,
37,
12
6,
12
0
200
1
9
uv_mode_probs
[9] [0..8]
102,
19, 66,
162,
182,
122,
35, 59,
128
10
1,
21,
10
7,
18
1,
19
2,
10
3,
19,
67,
12
5
0
18
86
30
2
201
0
7
seg_tree_probs
[0..6]
255,
255,
255,
255,
255,
255,
255
25
5,
25
5,
25
5,
25
0
18
95
31
1
HEVC
108
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
5,
25
5,
25
5,
25
5
201
7
3
seg_pred_probs
[0..2]
255,
255,
255
25
5,
25
5,
25
5
0
19
02
31
8
202
0
28
DUMMY
0, 0, 0,
0, 0, 0,
0, 0, 0,
0, 0, 0,
0, 0, 0,
0, 0, 0,
0, 0, 0,
0, 0, 0,
0, 0, 0
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
11
5
19
05
32
1
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
109
Alignm
ent
Ne
w
Offs
et
#
Byt
es
Description
Keyfra
me
defaul
ts
Inter frame
defaults
Capture At DV_CNT
State
count
er
EBB
Addr
ess
Coefficient counter EBB Address
4x
4
(K
F)
4x4
(INTE
R)
8x
8
(K
F)
8x8
(INTE
R)
16x
16
(KF)
16x1
6
(INTE
R)
32x
32
(KF)
32x3
2
(INTE
R)
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
CL
aligned
204
8
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
1
Stream-in formats for creating compressed header
The following memory surfaces are input to PAK for Compressed Header coding
i. Prob Diff Surface
In Probability Diff Surface, there are 1805 8-bit Probability Diffs. Each of them corresponding to a
Probability Diff in Compressed Header syntax. Although, for a given compressed header, not all the
Probability Diff would be coded (depends on update flag), Probability Diff Surface is fully populated with
1805 entries (1805*8 / 512 = 29 cachelines). The 1805 8-bit Probability Diffs are expected to follow
Compressed Header syntax order and fully packed.
ii. Compressed Header Syntax Surface
Each of the Compressed header Coding element (described in (2)) is represented by a 4-bit field. These
4-bit fields follows Compressed Header Syntax. Each of the field has a valid, Bin_probDiff_select,
Prob_select, Bin as described in the table below.
Description
Valid
Set to 1 if this is a valid Bin OR ProbabilityDiff field to code; Set to 0 to skip coding this field
Bin_ProbDiff_select
Set to 1 if Current field is a Bin (corresponding Prob, Bin are indicated by next 2 bits); Set to 0 if
Current field is Probability Diff (probability diff to be coded is located in probability surface -
ReMap)
Prob_Select
If current field is Bin, set to 1 if prob is 252; set to 0 if prob is 128
Bin
if current field is Bin, this is Bin value to be encoded
Compressed Header Syntax Surface is a fixed length surface. For syntax that should not be coded, valid
bit should be set to 0. Total length of Compressed Header syntax Surface has 4033 Coding elements
(16132 bits in 32 cachelines):
1805 Prob Diff and Prob Update flag
4 is_coeff_updated flag (per 4x4, 8x8, 16x16, 32x32)
5 control fields (MIN (tx_mode, ALLOW_32x32), tx_mode == TX_MODE_SELECT, use_compound_pred,
use_hybrid_pred)
HEVC
2
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Probability Statistics Counters Table
In VP9 encoding, statistic collection is required to utilize the Forward Adaptation feature, which can
substantially improve decoding performance because no intermediate computations based on
encountered tokens is necessary. After encoding a frame, the VP9 encoder writes a Statistics Counter in
the memory surface (HCP_IND_OBJ_BASE_ADDR_STATE: HCP VP9 PAK Probability Counter Streamout).
The counter written in the memory surface is the same order as the VP9 Compressed header format.
The Statistics Counters collect frame statistics per symbol. In the VP9 Encoder, the PAK engine is
responsible for statistics counter collection. The Kernel performs probability updates based on statistics
counter values.
Each counter has has an associated context according to the VP9 Specification/Model.
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
1
Probability Statistics Counters Table
Note: The following table is arranged such that each row corresponds to sixteen 32-bit counters. In other words, each row
corresponds to 512 bits (1 Cacheline). The VP9 Encoder PAK engine will have a total of 193 cacheline writers in the memory surface
(HCP_IND_OBJ_BASW_ADDR_STATE: HCP VP9 PAK Probability Counter Streamout) at the end of each frame.
For brevity, data in the table is abbreviated. A Context Legend table has been provided after the Probability Statistics Counters table
that explains the data in more detail.
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
ct_tx_8x8
ct_tx_16x16
ct_tx_32x32
[0]
[0]
[0]
[1]
[1]
[0]
[1]
[1]
[0]
[0]
[0]
[1]
[0]
[2]
[1]
[0]
[1]
[1]
[1]
[2]
[0]
[0]
[0]
[1]
[0]
[2]
[0]
[3]
[1]
[0]
[1]
[1]
R1
ct_tx_32x32
ct_coef
[1]
[2]
[1]
[3]
[T=0]
[B=0]
[R=0]
[CB=0]
[CT=0]
[N=0]
[T=0]
[B=0]
[R=0]
[CB=0]
[CT=0]
[N=1]
[T=0]
[B=0]
[R=0]
[CB=0]
[CT=0]
[N=2]
[T=0]
[B=0]
[R=0]
[CB=0]
[CT=0]
[N=3]
[T=0]
[B=0]
[R=0]
[CB=0]
[CT=1]
[N=0]
[T=0]
[B=0]
[R=0]
[CB=0]
[CT=1]
[N=1]
[T=0]
[B=0]
[R=0]
[CB=0]
[CT=1]
[N=2]
[T=0]
[B=0]
[R=0]
[CB=0]
[CT=1]
[N=3]
[T=0]
[B=0]
[R=0]
[CB=0]
[CT=2]
[N=0]
[T=0]
[B=0]
[R=0]
[CB=0]
[CT=2]
[N=1]
[T=0]
[B=0]
[R=0]
[CB=0]
[CT=2]
[N=2]
[T=0]
[B=0]
[R=0]
[CB=0]
[CT=2]
[N=3]
[T=0]
[B=0]
[R=0]
[CB=1]
[CT=0]
[N=0]
[T=0]
[B=0]
[R=0]
[CB=1]
[CT=0]
[N=1]
R2
ct_coef
[T=0]
[B=0]
[R=0]
[CB=1]
[CT=0]
[N=2]
[T=0]
[B=0]
[R=0]
[CB=1]
[CT=0]
[N=3]
[T=0]
[B=0]
[R=0]
[CB=1]
[CT=1]
[N=0]
[T=0]
[B=0]
[R=0]
[CB=1]
[CT=1]
[N=1]
[T=0]
[B=0]
[R=0]
[CB=1]
[CT=1]
[N=2]
[T=0]
[B=0]
[R=0]
[CB=1]
[CT=1]
[N=3]
[T=0]
[B=0]
[R=0]
[CB=1]
[CT=2]
[N=0]
[T=0]
[B=0]
[R=0]
[CB=1]
[CT=2]
[N=1]
[T=0]
[B=0]
[R=0]
[CB=1]
[CT=2]
[N=2]
[T=0]
[B=0]
[R=0]
[CB=1]
[CT=2]
[N=3]
[T=0]
[B=0]
[R=0]
[CB=1]
[CT=3]
[N=0]
[T=0]
[B=0]
[R=0]
[CB=1]
[CT=3]
[N=1]
[T=0]
[B=0]
[R=0]
[CB=1]
[CT=3]
[N=2]
[T=0]
[B=0]
[R=0]
[CB=1]
[CT=3]
[N=3]
[T=0]
[B=0]
[R=0]
[CB=1]
[CT=4]
[N=0]
[T=0]
[B=0]
[R=0]
[CB=1]
[CT=4]
[N=1]
HEVC
2
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R3
ct_coef
[T=0]
[B=0]
[R=0]
[CB=1]
[CT=4]
[N=2]
[T=0]
[B=0]
[R=0]
[CB=1]
[CT=4]
[N=3]
[T=0]
[B=0]
[R=0]
[CB=1]
[CT=5]
[N=0]
[T=0]
[B=0]
[R=0]
[CB=1]
[CT=5]
[N=1]
[T=0]
[B=0]
[R=0]
[CB=1]
[CT=5]
[N=2]
[T=0]
[B=0]
[R=0]
[CB=1]
[CT=5]
[N=3]
[T=0]
[B=0]
[R=0]
[CB=2]
[CT=0]
[N=0]
[T=0]
[B=0]
[R=0]
[CB=2]
[CT=0]
[N=1]
[T=0]
[B=0]
[R=0]
[CB=2]
[CT=0]
[N=2]
[T=0]
[B=0]
[R=0]
[CB=2]
[CT=0]
[N=3]
[T=0]
[B=0]
[R=0]
[CB=2]
[CT=1]
[N=0]
[T=0]
[B=0]
[R=0]
[CB=2]
[CT=1]
[N=1]
[T=0]
[B=0]
[R=0]
[CB=2]
[CT=1]
[N=2]
[T=0]
[B=0]
[R=0]
[CB=2]
[CT=1]
[N=3]
[T=0]
[B=0]
[R=0]
[CB=2]
[CT=2]
[N=0]
[T=0]
[B=0]
[R=0]
[CB=2]
[CT=2]
[N=1]
R4
ct_coef
[T=0]
[B=0]
[R=0]
[CB=2]
[CT=2]
[N=2]
[T=0]
[B=0]
[R=0]
[CB=2]
[CT=2]
[N=3]
[T=0]
[B=0]
[R=0]
[CB=2]
[CT=3]
[N=0]
[T=0]
[B=0]
[R=0]
[CB=2]
[CT=3]
[N=1]
[T=0]
[B=0]
[R=0]
[CB=2]
[CT=3]
[N=2]
[T=0]
[B=0]
[R=0]
[CB=2]
[CT=3]
[N=3]
[T=0]
[B=0]
[R=0]
[CB=2]
[CT=4]
[N=0]
[T=0]
[B=0]
[R=0]
[CB=2]
[CT=4]
[N=1]
[T=0]
[B=0]
[R=0]
[CB=2]
[CT=4]
[N=2]
[T=0]
[B=0]
[R=0]
[CB=2]
[CT=4]
[N=3]
[T=0]
[B=0]
[R=0]
[CB=2]
[CT=5]
[N=0]
[T=0]
[B=0]
[R=0]
[CB=2]
[CT=5]
[N=1]
[T=0]
[B=0]
[R=0]
[CB=2]
[CT=5]
[N=2]
[T=0]
[B=0]
[R=0]
[CB=2]
[CT=5]
[N=3]
[T=0]
[B=0]
[R=0]
[CB=3]
[CT=0]
[N=0]
[T=0]
[B=0]
[R=0]
[CB=3]
[CT=0]
[N=1]
R5
ct_coef
[T=0]
[B=0]
[R=0]
[CB=3]
[CT=0]
[N=2]
[T=0]
[B=0]
[R=0]
[CB=3]
[CT=0]
[N=3]
[T=0]
[B=0]
[R=0]
[CB=3]
[CT=1]
[N=0]
[T=0]
[B=0]
[R=0]
[CB=3]
[CT=1]
[N=1]
[T=0]
[B=0]
[R=0]
[CB=3]
[CT=1]
[N=2]
[T=0]
[B=0]
[R=0]
[CB=3]
[CT=1]
[N=3]
[T=0]
[B=0]
[R=0]
[CB=3]
[CT=2]
[N=0]
[T=0]
[B=0]
[R=0]
[CB=3]
[CT=2]
[N=1]
[T=0]
[B=0]
[R=0]
[CB=3]
[CT=2]
[N=2]
[T=0]
[B=0]
[R=0]
[CB=3]
[CT=2]
[N=3]
[T=0]
[B=0]
[R=0]
[CB=3]
[CT=3]
[N=0]
[T=0]
[B=0]
[R=0]
[CB=3]
[CT=3]
[N=1]
[T=0]
[B=0]
[R=0]
[CB=3]
[CT=3]
[N=2]
[T=0]
[B=0]
[R=0]
[CB=3]
[CT=3]
[N=3]
[T=0]
[B=0]
[R=0]
[CB=3]
[CT=4]
[N=0]
[T=0]
[B=0]
[R=0]
[CB=3]
[CT=4]
[N=1]
R6
ct_coef
[T=0]
[T=0]
[T=0]
[T=0]
[T=0]
[T=0]
[T=0]
[T=0]
[T=0]
[T=0]
[T=0]
[T=0]
[T=0]
[T=0]
[T=0]
[T=0]
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
3
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[B=0]
[R=0]
[CB=3]
[CT=4]
[N=2]
[B=0]
[R=0]
[CB=3]
[CT=4]
[N=3]
[B=0]
[R=0]
[CB=3]
[CT=5]
[N=0]
[B=0]
[R=0]
[CB=3]
[CT=5]
[N=1]
[B=0]
[R=0]
[CB=3]
[CT=5]
[N=2]
[B=0]
[R=0]
[CB=3]
[CT=5]
[N=3]
[B=0]
[R=0]
[CB=4]
[CT=0]
[N=0]
[B=0]
[R=0]
[CB=4]
[CT=0]
[N=1]
[B=0]
[R=0]
[CB=4]
[CT=0]
[N=2]
[B=0]
[R=0]
[CB=4]
[CT=0]
[N=3]
[B=0]
[R=0]
[CB=4]
[CT=1]
[N=0]
[B=0]
[R=0]
[CB=4]
[CT=1]
[N=1]
[B=0]
[R=0]
[CB=4]
[CT=1]
[N=2]
[B=0]
[R=0]
[CB=4]
[CT=1]
[N=3]
[B=0]
[R=0]
[CB=4]
[CT=2]
[N=0]
[B=0]
[R=0]
[CB=4]
[CT=2]
[N=1]
R7
ct_coef
[T=0]
[B=0]
[R=0]
[CB=4]
[CT=2]
[N=2]
[T=0]
[B=0]
[R=0]
[CB=4]
[CT=2]
[N=3]
[T=0]
[B=0]
[R=0]
[CB=4]
[CT=3]
[N=0]
[T=0]
[B=0]
[R=0]
[CB=4]
[CT=3]
[N=1]
[T=0]
[B=0]
[R=0]
[CB=4]
[CT=3]
[N=2]
[T=0]
[B=0]
[R=0]
[CB=4]
[CT=3]
[N=3]
[T=0]
[B=0]
[R=0]
[CB=4]
[CT=4]
[N=0]
[T=0]
[B=0]
[R=0]
[CB=4]
[CT=4]
[N=1]
[T=0]
[B=0]
[R=0]
[CB=4]
[CT=4]
[N=2]
[T=0]
[B=0]
[R=0]
[CB=4]
[CT=4]
[N=3]
[T=0]
[B=0]
[R=0]
[CB=4]
[CT=5]
[N=0]
[T=0]
[B=0]
[R=0]
[CB=4]
[CT=5]
[N=1]
[T=0]
[B=0]
[R=0]
[CB=4]
[CT=5]
[N=2]
[T=0]
[B=0]
[R=0]
[CB=4]
[CT=5]
[N=3]
[T=0]
[B=0]
[R=0]
[CB=5]
[CT=0]
[N=0]
[T=0]
[B=0]
[R=0]
[CB=5]
[CT=0]
[N=1]
R8
ct_coef
[T=0]
[B=0]
[R=0]
[CB=5]
[CT=0]
[N=2]
[T=0]
[B=0]
[R=0]
[CB=5]
[CT=0]
[N=3]
[T=0]
[B=0]
[R=0]
[CB=5]
[CT=1]
[N=0]
[T=0]
[B=0]
[R=0]
[CB=5]
[CT=1]
[N=1]
[T=0]
[B=0]
[R=0]
[CB=5]
[CT=1]
[N=2]
[T=0]
[B=0]
[R=0]
[CB=5]
[CT=1]
[N=3]
[T=0]
[B=0]
[R=0]
[CB=5]
[CT=2]
[N=0]
[T=0]
[B=0]
[R=0]
[CB=5]
[CT=2]
[N=1]
[T=0]
[B=0]
[R=0]
[CB=5]
[CT=2]
[N=2]
[T=0]
[B=0]
[R=0]
[CB=5]
[CT=2]
[N=3]
[T=0]
[B=0]
[R=0]
[CB=5]
[CT=3]
[N=0]
[T=0]
[B=0]
[R=0]
[CB=5]
[CT=3]
[N=1]
[T=0]
[B=0]
[R=0]
[CB=5]
[CT=3]
[N=2]
[T=0]
[B=0]
[R=0]
[CB=5]
[CT=3]
[N=3]
[T=0]
[B=0]
[R=0]
[CB=5]
[CT=4]
[N=0]
[T=0]
[B=0]
[R=0]
[CB=5]
[CT=4]
[N=1]
R9
ct_coef
[T=0]
[B=0]
[R=0]
[T=0]
[B=0]
[R=0]
[T=0]
[B=0]
[R=0]
[T=0]
[B=0]
[R=0]
[T=0]
[B=0]
[R=0]
[T=0]
[B=0]
[R=0]
[T=0]
[B=0]
[R=1]
[T=0]
[B=0]
[R=1]
[T=0]
[B=0]
[R=1]
[T=0]
[B=0]
[R=1]
[T=0]
[B=0]
[R=1]
[T=0]
[B=0]
[R=1]
[T=0]
[B=0]
[R=1]
[T=0]
[B=0]
[R=1]
[T=0]
[B=0]
[R=1]
[T=0]
[B=0]
[R=1]
HEVC
4
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[CB=5]
[CT=4]
[N=2]
[CB=5]
[CT=4]
[N=3]
[CB=5]
[CT=5]
[N=0]
[CB=5]
[CT=5]
[N=1]
[CB=5]
[CT=5]
[N=2]
[CB=5]
[CT=5]
[N=3]
[CB=0]
[CT=0]
[N=0]
[CB=0]
[CT=0]
[N=1]
[CB=0]
[CT=0]
[N=2]
[CB=0]
[CT=0]
[N=3]
[CB=0]
[CT=1]
[N=0]
[CB=0]
[CT=1]
[N=1]
[CB=0]
[CT=1]
[N=2]
[CB=0]
[CT=1]
[N=3]
[CB=0]
[CT=2]
[N=0]
[CB=0]
[CT=2]
[N=1]
R10
ct_coef
[T=0]
[B=0]
[R=1]
[CB=0]
[CT=2]
[N=2]
[T=0]
[B=0]
[R=1]
[CB=0]
[CT=2]
[N=3]
[T=0]
[B=0]
[R=1]
[CB=1]
[CT=0]
[N=0]
[T=0]
[B=0]
[R=1]
[CB=1]
[CT=0]
[N=1]
[T=0]
[B=0]
[R=1]
[CB=1]
[CT=0]
[N=2]
[T=0]
[B=0]
[R=1]
[CB=1]
[CT=0]
[N=3]
[T=0]
[B=0]
[R=1]
[CB=1]
[CT=1]
[N=0]
[T=0]
[B=0]
[R=1]
[CB=1]
[CT=1]
[N=1]
[T=0]
[B=0]
[R=1]
[CB=1]
[CT=1]
[N=2]
[T=0]
[B=0]
[R=1]
[CB=1]
[CT=1]
[N=3]
[T=0]
[B=0]
[R=1]
[CB=1]
[CT=2]
[N=0]
[T=0]
[B=0]
[R=1]
[CB=1]
[CT=2]
[N=1]
[T=0]
[B=0]
[R=1]
[CB=1]
[CT=2]
[N=2]
[T=0]
[B=0]
[R=1]
[CB=1]
[CT=2]
[N=3]
[T=0]
[B=0]
[R=1]
[CB=1]
[CT=3]
[N=0]
[T=0]
[B=0]
[R=1]
[CB=1]
[CT=3]
[N=1]
R11
ct_coef
[T=0]
[B=0]
[R=1]
[CB=1]
[CT=3]
[N=2]
[T=0]
[B=0]
[R=1]
[CB=1]
[CT=3]
[N=3]
[T=0]
[B=0]
[R=1]
[CB=1]
[CT=4]
[N=0]
[T=0]
[B=0]
[R=1]
[CB=1]
[CT=4]
[N=1]
[T=0]
[B=0]
[R=1]
[CB=1]
[CT=4]
[N=2]
[T=0]
[B=0]
[R=1]
[CB=1]
[CT=4]
[N=3]
[T=0]
[B=0]
[R=1]
[CB=1]
[CT=5]
[N=0]
[T=0]
[B=0]
[R=1]
[CB=1]
[CT=5]
[N=1]
[T=0]
[B=0]
[R=1]
[CB=1]
[CT=5]
[N=2]
[T=0]
[B=0]
[R=1]
[CB=1]
[CT=5]
[N=3]
[T=0]
[B=0]
[R=1]
[CB=2]
[CT=0]
[N=0]
[T=0]
[B=0]
[R=1]
[CB=2]
[CT=0]
[N=1]
[T=0]
[B=0]
[R=1]
[CB=2]
[CT=0]
[N=2]
[T=0]
[B=0]
[R=1]
[CB=2]
[CT=0]
[N=3]
[T=0]
[B=0]
[R=1]
[CB=2]
[CT=1]
[N=0]
[T=0]
[B=0]
[R=1]
[CB=2]
[CT=1]
[N=1]
R12
ct_coef
[T=0]
[B=0]
[R=1]
[CB=2]
[CT=1]
[T=0]
[B=0]
[R=1]
[CB=2]
[T=0]
[B=0]
[R=1]
[CB=2]
[T=0]
[B=0]
[R=1]
[CB=2]
[T=0]
[B=0]
[R=1]
[CB=2]
[T=0]
[B=0]
[R=1]
[CB=2]
[T=0]
[B=0]
[R=1]
[CB=2]
[T=0]
[B=0]
[R=1]
[CB=2]
[T=0]
[B=0]
[R=1]
[CB=2]
[T=0]
[B=0]
[R=1]
[CB=2]
[T=0]
[B=0]
[R=1]
[CB=2]
[T=0]
[B=0]
[R=1]
[CB=2]
[T=0]
[B=0]
[R=1]
[CB=2]
[T=0]
[B=0]
[R=1]
[CB=2]
[T=0]
[B=0]
[R=1]
[CB=2]
[T=0]
[B=0]
[R=1]
[CB=2]
[CT=5]
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
5
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[N=2]
[CT=1]
[N=3]
[CT=2]
[N=0]
[CT=2]
[N=1]
[CT=2]
[N=2]
[CT=2]
[N=3]
[CT=3]
[N=0]
[CT=3]
[N=1]
[CT=3]
[N=2]
[CT=3]
[N=3]
[CT=4]
[N=0]
[CT=4]
[N=1]
[CT=4]
[N=2]
[CT=4]
[N=3]
[CT=5]
[N=0]
[N=1]
R13
ct_coef
[T=0]
[B=0]
[R=1]
[CB=2]
[CT=5]
[N=2]
[T=0]
[B=0]
[R=1]
[CB=2]
[CT=5]
[N=3]
[T=0]
[B=0]
[R=1]
[CB=3]
[CT=0]
[N=0]
[T=0]
[B=0]
[R=1]
[CB=3]
[CT=0]
[N=1]
[T=0]
[B=0]
[R=1]
[CB=3]
[CT=0]
[N=2]
[T=0]
[B=0]
[R=1]
[CB=3]
[CT=0]
[N=3]
[T=0]
[B=0]
[R=1]
[CB=3]
[CT=1]
[N=0]
[T=0]
[B=0]
[R=1]
[CB=3]
[CT=1]
[N=1]
[T=0]
[B=0]
[R=1]
[CB=3]
[CT=1]
[N=2]
[T=0]
[B=0]
[R=1]
[CB=3]
[CT=1]
[N=3]
[T=0]
[B=0]
[R=1]
[CB=3]
[CT=2]
[N=0]
[T=0]
[B=0]
[R=1]
[CB=3]
[CT=2]
[N=1]
[T=0]
[B=0]
[R=1]
[CB=3]
[CT=2]
[N=2]
[T=0]
[B=0]
[R=1]
[CB=3]
[CT=2]
[N=3]
[T=0]
[B=0]
[R=1]
[CB=3]
[CT=3]
[N=0]
[T=0]
[B=0]
[R=1]
[CB=3]
[CT=3]
[N=1]
R14
ct_coef
[T=0]
[B=0]
[R=1]
[CB=3]
[CT=3]
[N=2]
[T=0]
[B=0]
[R=1]
[CB=3]
[CT=3]
[N=3]
[T=0]
[B=0]
[R=1]
[CB=3]
[CT=4]
[N=0]
[T=0]
[B=0]
[R=1]
[CB=3]
[CT=4]
[N=1]
[T=0]
[B=0]
[R=1]
[CB=3]
[CT=4]
[N=2]
[T=0]
[B=0]
[R=1]
[CB=3]
[CT=4]
[N=3]
[T=0]
[B=0]
[R=1]
[CB=3]
[CT=5]
[N=0]
[T=0]
[B=0]
[R=1]
[CB=3]
[CT=5]
[N=1]
[T=0]
[B=0]
[R=1]
[CB=3]
[CT=5]
[N=2]
[T=0]
[B=0]
[R=1]
[CB=3]
[CT=5]
[N=3]
[T=0]
[B=0]
[R=1]
[CB=4]
[CT=0]
[N=0]
[T=0]
[B=0]
[R=1]
[CB=4]
[CT=0]
[N=1]
[T=0]
[B=0]
[R=1]
[CB=4]
[CT=0]
[N=2]
[T=0]
[B=0]
[R=1]
[CB=4]
[CT=0]
[N=3]
[T=0]
[B=0]
[R=1]
[CB=4]
[CT=1]
[N=0]
[T=0]
[B=0]
[R=1]
[CB=4]
[CT=1]
[N=1]
R15
ct_coef
[T=0]
[B=0]
[R=1]
[CB=4]
[CT=1]
[N=2]
[T=0]
[B=0]
[R=1]
[CB=4]
[CT=1]
[T=0]
[B=0]
[R=1]
[CB=4]
[CT=2]
[T=0]
[B=0]
[R=1]
[CB=4]
[CT=2]
[T=0]
[B=0]
[R=1]
[CB=4]
[CT=2]
[T=0]
[B=0]
[R=1]
[CB=4]
[CT=2]
[T=0]
[B=0]
[R=1]
[CB=4]
[CT=3]
[T=0]
[B=0]
[R=1]
[CB=4]
[CT=3]
[T=0]
[B=0]
[R=1]
[CB=4]
[CT=3]
[T=0]
[B=0]
[R=1]
[CB=4]
[CT=3]
[T=0]
[B=0]
[R=1]
[CB=4]
[CT=4]
[N=0]
[T=0]
[B=0]
[R=1]
[CB=4]
[CT=4]
[N=1]
[T=0]
[B=0]
[R=1]
[CB=4]
[CT=4]
[T=0]
[B=0]
[R=1]
[CB=4]
[CT=4]
[T=0]
[B=0]
[R=1]
[CB=4]
[CT=5]
[T=0]
[B=0]
[R=1]
[CB=4]
[CT=5]
[N=1]
HEVC
6
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[N=3]
[N=0]
[N=1]
[N=2]
[N=3]
[N=0]
[N=1]
[N=2]
[N=3]
[N=2]
[N=3]
[N=0]
R16
ct_coef
[T=0]
[B=0]
[R=1]
[CB=4]
[CT=5]
[N=2]
[T=0]
[B=0]
[R=1]
[CB=4]
[CT=5]
[N=3]
[T=0]
[B=0]
[R=1]
[CB=5]
[CT=0]
[N=0]
[T=0]
[B=0]
[R=1]
[CB=5]
[CT=0]
[N=1]
[T=0]
[B=0]
[R=1]
[CB=5]
[CT=0]
[N=2]
[T=0]
[B=0]
[R=1]
[CB=5]
[CT=0]
[N=3]
[T=0]
[B=0]
[R=1]
[CB=5]
[CT=1]
[N=0]
[T=0]
[B=0]
[R=1]
[CB=5]
[CT=1]
[N=1]
[T=0]
[B=0]
[R=1]
[CB=5]
[CT=1]
[N=2]
[T=0]
[B=0]
[R=1]
[CB=5]
[CT=1]
[N=3]
[T=0]
[B=0]
[R=1]
[CB=5]
[CT=2]
[N=0]
[T=0]
[B=0]
[R=1]
[CB=5]
[CT=2]
[N=1]
[T=0]
[B=0]
[R=1]
[CB=5]
[CT=2]
[N=2]
[T=0]
[B=0]
[R=1]
[CB=5]
[CT=2]
[N=3]
[T=0]
[B=0]
[R=1]
[CB=5]
[CT=3]
[N=0]
[T=0]
[B=0]
[R=1]
[CB=5]
[CT=3]
[N=1]
R17
ct_coef
[T=0]
[B=0]
[R=1]
[CB=5]
[CT=3]
[N=2]
[T=0]
[B=0]
[R=1]
[CB=5]
[CT=3]
[N=3]
[T=0]
[B=0]
[R=1]
[CB=5]
[CT=4]
[N=0]
[T=0]
[B=0]
[R=1]
[CB=5]
[CT=4]
[N=1]
[T=0]
[B=0]
[R=1]
[CB=5]
[CT=4]
[N=2]
[T=0]
[B=0]
[R=1]
[CB=5]
[CT=4]
[N=3]
[T=0]
[B=0]
[R=1]
[CB=5]
[CT=5]
[N=0]
[T=0]
[B=0]
[R=1]
[CB=5]
[CT=5]
[N=1]
[T=0]
[B=0]
[R=1]
[CB=5]
[CT=5]
[N=2]
[T=0]
[B=0]
[R=1]
[CB=5]
[CT=5]
[N=3]
[T=0]
[B=1]
[R=0]
[CB=0]
[CT=0]
[N=0]
[T=0]
[B=1]
[R=0]
[CB=0]
[CT=0]
[N=1]
[T=0]
[B=1]
[R=0]
[CB=0]
[CT=0]
[N=2]
[T=0]
[B=1]
[R=0]
[CB=0]
[CT=0]
[N=3]
[T=0]
[B=1]
[R=0]
[CB=0]
[CT=1]
[N=0]
[T=0]
[B=1]
[R=0]
[CB=0]
[CT=1]
[N=1]
R18
ct_coef
[T=0]
[B=1]
[R=0]
[CB=0]
[CT=1]
[N=2]
[T=0]
[B=1]
[R=0]
[CB=0]
[CT=1]
[N=3]
[T=0]
[B=1]
[R=0]
[CB=0]
[CT=2]
[N=0]
[T=0]
[B=1]
[R=0]
[CB=0]
[CT=2]
[N=1]
[T=0]
[B=1]
[R=0]
[CB=0]
[CT=2]
[N=2]
[T=0]
[B=1]
[R=0]
[CB=0]
[CT=2]
[N=3]
[T=0]
[B=1]
[R=0]
[CB=1]
[CT=0]
[N=0]
[T=0]
[B=1]
[R=0]
[CB=1]
[CT=0]
[N=1]
[T=0]
[B=1]
[R=0]
[CB=1]
[CT=0]
[N=2]
[T=0]
[B=1]
[R=0]
[CB=1]
[CT=0]
[N=3]
[T=0]
[B=1]
[R=0]
[CB=1]
[CT=1]
[N=0]
[T=0]
[B=1]
[R=0]
[CB=1]
[CT=1]
[N=1]
[T=0]
[B=1]
[R=0]
[CB=1]
[CT=1]
[N=2]
[T=0]
[B=1]
[R=0]
[CB=1]
[CT=1]
[N=3]
[T=0]
[B=1]
[R=0]
[CB=1]
[CT=2]
[N=0]
[T=0]
[B=1]
[R=0]
[CB=1]
[CT=2]
[N=1]
R19
ct_coef
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
7
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[T=0]
[B=1]
[R=0]
[CB=1]
[CT=2]
[N=2]
[T=0]
[B=1]
[R=0]
[CB=1]
[CT=2]
[N=3]
[T=0]
[B=1]
[R=0]
[CB=1]
[CT=3]
[N=0]
[T=0]
[B=1]
[R=0]
[CB=1]
[CT=3]
[N=1]
[T=0]
[B=1]
[R=0]
[CB=1]
[CT=3]
[N=2]
[T=0]
[B=1]
[R=0]
[CB=1]
[CT=3]
[N=3]
[T=0]
[B=1]
[R=0]
[CB=1]
[CT=4]
[N=0]
[T=0]
[B=1]
[R=0]
[CB=1]
[CT=4]
[N=1]
[T=0]
[B=1]
[R=0]
[CB=1]
[CT=4]
[N=2]
[T=0]
[B=1]
[R=0]
[CB=1]
[CT=4]
[N=3]
[T=0]
[B=1]
[R=0]
[CB=1]
[CT=5]
[N=0]
[T=0]
[B=1]
[R=0]
[CB=1]
[CT=5]
[N=1]
[T=0]
[B=1]
[R=0]
[CB=1]
[CT=5]
[N=2]
[T=0]
[B=1]
[R=0]
[CB=1]
[CT=5]
[N=3]
[T=0]
[B=1]
[R=0]
[CB=2]
[CT=0]
[N=0]
[T=0]
[B=1]
[R=0]
[CB=2]
[CT=0]
[N=1]
R20
ct_coef
[T=0]
[B=1]
[R=0]
[CB=2]
[CT=0]
[N=2]
[T=0]
[B=1]
[R=0]
[CB=2]
[CT=0]
[N=3]
[T=0]
[B=1]
[R=0]
[CB=2]
[CT=1]
[N=0]
[T=0]
[B=1]
[R=0]
[CB=2]
[CT=1]
[N=1]
[T=0]
[B=1]
[R=0]
[CB=2]
[CT=1]
[N=2]
[T=0]
[B=1]
[R=0]
[CB=2]
[CT=1]
[N=3]
[T=0]
[B=1]
[R=0]
[CB=2]
[CT=2]
[N=0]
[T=0]
[B=1]
[R=0]
[CB=2]
[CT=2]
[N=1]
[T=0]
[B=1]
[R=0]
[CB=2]
[CT=2]
[N=2]
[T=0]
[B=1]
[R=0]
[CB=2]
[CT=2]
[N=3]
[T=0]
[B=1]
[R=0]
[CB=2]
[CT=3]
[N=0]
[T=0]
[B=1]
[R=0]
[CB=2]
[CT=3]
[N=1]
[T=0]
[B=1]
[R=0]
[CB=2]
[CT=3]
[N=2]
[T=0]
[B=1]
[R=0]
[CB=2]
[CT=3]
[N=3]
[T=0]
[B=1]
[R=0]
[CB=2]
[CT=4]
[N=0]
[T=0]
[B=1]
[R=0]
[CB=2]
[CT=4]
[N=1]
R21
ct_coef
[T=0]
[B=1]
[R=0]
[CB=2]
[CT=4]
[N=2]
[T=0]
[B=1]
[R=0]
[CB=2]
[CT=4]
[N=3]
[T=0]
[B=1]
[R=0]
[CB=2]
[CT=5]
[N=0]
[T=0]
[B=1]
[R=0]
[CB=2]
[CT=5]
[N=1]
[T=0]
[B=1]
[R=0]
[CB=2]
[CT=5]
[N=2]
[T=0]
[B=1]
[R=0]
[CB=2]
[CT=5]
[N=3]
[T=0]
[B=1]
[R=0]
[CB=3]
[CT=0]
[N=0]
[T=0]
[B=1]
[R=0]
[CB=3]
[CT=0]
[N=1]
[T=0]
[B=1]
[R=0]
[CB=3]
[CT=0]
[N=2]
[T=0]
[B=1]
[R=0]
[CB=3]
[CT=0]
[N=3]
[T=0]
[B=1]
[R=0]
[CB=3]
[CT=1]
[N=0]
[T=0]
[B=1]
[R=0]
[CB=3]
[CT=1]
[N=1]
[T=0]
[B=1]
[R=0]
[CB=3]
[CT=1]
[N=2]
[T=0]
[B=1]
[R=0]
[CB=3]
[CT=1]
[N=3]
[T=0]
[B=1]
[R=0]
[CB=3]
[CT=2]
[N=0]
[T=0]
[B=1]
[R=0]
[CB=3]
[CT=2]
[N=1]
R22
ct_coef
[T=0]
[B=1]
[T=0]
[B=1]
[T=0]
[B=1]
[T=0]
[B=1]
[T=0]
[B=1]
[T=0]
[B=1]
[T=0]
[B=1]
[T=0]
[B=1]
[T=0]
[B=1]
[T=0]
[B=1]
[T=0]
[B=1]
[T=0]
[B=1]
[T=0]
[B=1]
[T=0]
[B=1]
[T=0]
[B=1]
[T=0]
[B=1]
HEVC
8
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[R=0]
[CB=3]
[CT=2]
[N=2]
[R=0]
[CB=3]
[CT=2]
[N=3]
[R=0]
[CB=3]
[CT=3]
[N=0]
[R=0]
[CB=3]
[CT=3]
[N=1]
[R=0]
[CB=3]
[CT=3]
[N=2]
[R=0]
[CB=3]
[CT=3]
[N=3]
[R=0]
[CB=3]
[CT=4]
[N=0]
[R=0]
[CB=3]
[CT=4]
[N=1]
[R=0]
[CB=3]
[CT=4]
[N=2]
[R=0]
[CB=3]
[CT=4]
[N=3]
[R=0]
[CB=3]
[CT=5]
[N=0]
[R=0]
[CB=3]
[CT=5]
[N=1]
[R=0]
[CB=3]
[CT=5]
[N=2]
[R=0]
[CB=3]
[CT=5]
[N=3]
[R=0]
[CB=4]
[CT=0]
[N=0]
[R=0]
[CB=4]
[CT=0]
[N=1]
R23
ct_coef
[T=0]
[B=1]
[R=0]
[CB=4]
[CT=0]
[N=2]
[T=0]
[B=1]
[R=0]
[CB=4]
[CT=0]
[N=3]
[T=0]
[B=1]
[R=0]
[CB=4]
[CT=1]
[N=0]
[T=0]
[B=1]
[R=0]
[CB=4]
[CT=1]
[N=1]
[T=0]
[B=1]
[R=0]
[CB=4]
[CT=1]
[N=2]
[T=0]
[B=1]
[R=0]
[CB=4]
[CT=1]
[N=3]
[T=0]
[B=1]
[R=0]
[CB=4]
[CT=2]
[N=0]
[T=0]
[B=1]
[R=0]
[CB=4]
[CT=2]
[N=1]
[T=0]
[B=1]
[R=0]
[CB=4]
[CT=2]
[N=2]
[T=0]
[B=1]
[R=0]
[CB=4]
[CT=2]
[N=3]
[T=0]
[B=1]
[R=0]
[CB=4]
[CT=3]
[N=0]
[T=0]
[B=1]
[R=0]
[CB=4]
[CT=3]
[N=1]
[T=0]
[B=1]
[R=0]
[CB=4]
[CT=3]
[N=2]
[T=0]
[B=1]
[R=0]
[CB=4]
[CT=3]
[N=3]
[T=0]
[B=1]
[R=0]
[CB=4]
[CT=4]
[N=0]
[T=0]
[B=1]
[R=0]
[CB=4]
[CT=4]
[N=1]
R24
ct_coef
[T=0]
[B=1]
[R=0]
[CB=4]
[CT=4]
[N=2]
[T=0]
[B=1]
[R=0]
[CB=4]
[CT=4]
[N=3]
[T=0]
[B=1]
[R=0]
[CB=4]
[CT=5]
[N=0]
[T=0]
[B=1]
[R=0]
[CB=4]
[CT=5]
[N=1]
[T=0]
[B=1]
[R=0]
[CB=4]
[CT=5]
[N=2]
[T=0]
[B=1]
[R=0]
[CB=4]
[CT=5]
[N=3]
[T=0]
[B=1]
[R=0]
[CB=5]
[CT=0]
[N=0]
[T=0]
[B=1]
[R=0]
[CB=5]
[CT=0]
[N=1]
[T=0]
[B=1]
[R=0]
[CB=5]
[CT=0]
[N=2]
[T=0]
[B=1]
[R=0]
[CB=5]
[CT=0]
[N=3]
[T=0]
[B=1]
[R=0]
[CB=5]
[CT=1]
[N=0]
[T=0]
[B=1]
[R=0]
[CB=5]
[CT=1]
[N=1]
[T=0]
[B=1]
[R=0]
[CB=5]
[CT=1]
[N=2]
[T=0]
[B=1]
[R=0]
[CB=5]
[CT=1]
[N=3]
[T=0]
[B=1]
[R=0]
[CB=5]
[CT=2]
[N=0]
[T=0]
[B=1]
[R=0]
[CB=5]
[CT=2]
[N=1]
R25
ct_coef
[T=0]
[B=1]
[R=0]
[CB=5]
[T=0]
[B=1]
[R=0]
[T=0]
[B=1]
[R=0]
[T=0]
[B=1]
[R=0]
[T=0]
[B=1]
[R=0]
[T=0]
[B=1]
[R=0]
[T=0]
[B=1]
[R=0]
[T=0]
[B=1]
[R=0]
[T=0]
[B=1]
[R=0]
[T=0]
[B=1]
[R=0]
[T=0]
[B=1]
[R=0]
[T=0]
[B=1]
[R=0]
[T=0]
[B=1]
[R=0]
[T=0]
[B=1]
[R=0]
[T=0]
[B=1]
[R=1]
[T=0]
[B=1]
[R=1]
[CB=0]
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
9
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[CT=2]
[N=2]
[CB=5]
[CT=2]
[N=3]
[CB=5]
[CT=3]
[N=0]
[CB=5]
[CT=3]
[N=1]
[CB=5]
[CT=3]
[N=2]
[CB=5]
[CT=3]
[N=3]
[CB=5]
[CT=4]
[N=0]
[CB=5]
[CT=4]
[N=1]
[CB=5]
[CT=4]
[N=2]
[CB=5]
[CT=4]
[N=3]
[CB=5]
[CT=5]
[N=0]
[CB=5]
[CT=5]
[N=1]
[CB=5]
[CT=5]
[N=2]
[CB=5]
[CT=5]
[N=3]
[CB=0]
[CT=0]
[N=0]
[CT=0]
[N=1]
R26
ct_coef
[T=0]
[B=1]
[R=1]
[CB=0]
[CT=0]
[N=2]
[T=0]
[B=1]
[R=1]
[CB=0]
[CT=0]
[N=3]
[T=0]
[B=1]
[R=1]
[CB=0]
[CT=1]
[N=0]
[T=0]
[B=1]
[R=1]
[CB=0]
[CT=1]
[N=1]
[T=0]
[B=1]
[R=1]
[CB=0]
[CT=1]
[N=2]
[T=0]
[B=1]
[R=1]
[CB=0]
[CT=1]
[N=3]
[T=0]
[B=1]
[R=1]
[CB=0]
[CT=2]
[N=0]
[T=0]
[B=1]
[R=1]
[CB=0]
[CT=2]
[N=1]
[T=0]
[B=1]
[R=1]
[CB=0]
[CT=2]
[N=2]
[T=0]
[B=1]
[R=1]
[CB=0]
[CT=2]
[N=3]
[T=0]
[B=1]
[R=1]
[CB=1]
[CT=0]
[N=0]
[T=0]
[B=1]
[R=1]
[CB=1]
[CT=0]
[N=1]
[T=0]
[B=1]
[R=1]
[CB=1]
[CT=0]
[N=2]
[T=0]
[B=1]
[R=1]
[CB=1]
[CT=0]
[N=3]
[T=0]
[B=1]
[R=1]
[CB=1]
[CT=1]
[N=0]
[T=0]
[B=1]
[R=1]
[CB=1]
[CT=1]
[N=1]
R27
ct_coef
[T=0]
[B=1]
[R=1]
[CB=1]
[CT=1]
[N=2]
[T=0]
[B=1]
[R=1]
[CB=1]
[CT=1]
[N=3]
[T=0]
[B=1]
[R=1]
[CB=1]
[CT=2]
[N=0]
[T=0]
[B=1]
[R=1]
[CB=1]
[CT=2]
[N=1]
[T=0]
[B=1]
[R=1]
[CB=1]
[CT=2]
[N=2]
[T=0]
[B=1]
[R=1]
[CB=1]
[CT=2]
[N=3]
[T=0]
[B=1]
[R=1]
[CB=1]
[CT=3]
[N=0]
[T=0]
[B=1]
[R=1]
[CB=1]
[CT=3]
[N=1]
[T=0]
[B=1]
[R=1]
[CB=1]
[CT=3]
[N=2]
[T=0]
[B=1]
[R=1]
[CB=1]
[CT=3]
[N=3]
[T=0]
[B=1]
[R=1]
[CB=1]
[CT=4]
[N=0]
[T=0]
[B=1]
[R=1]
[CB=1]
[CT=4]
[N=1]
[T=0]
[B=1]
[R=1]
[CB=1]
[CT=4]
[N=2]
[T=0]
[B=1]
[R=1]
[CB=1]
[CT=4]
[N=3]
[T=0]
[B=1]
[R=1]
[CB=1]
[CT=5]
[N=0]
[T=0]
[B=1]
[R=1]
[CB=1]
[CT=5]
[N=1]
R28
ct_coef
[T=0]
[B=1]
[R=1]
[CB=1]
[CT=5]
[N=2]
[T=0]
[B=1]
[R=1]
[CB=1]
[T=0]
[B=1]
[R=1]
[CB=2]
[T=0]
[B=1]
[R=1]
[CB=2]
[T=0]
[B=1]
[R=1]
[CB=2]
[T=0]
[B=1]
[R=1]
[CB=2]
[T=0]
[B=1]
[R=1]
[CB=2]
[T=0]
[B=1]
[R=1]
[CB=2]
[T=0]
[B=1]
[R=1]
[CB=2]
[T=0]
[B=1]
[R=1]
[CB=2]
[T=0]
[B=1]
[R=1]
[CB=2]
[CT=2]
[T=0]
[B=1]
[R=1]
[CB=2]
[CT=2]
[T=0]
[B=1]
[R=1]
[CB=2]
[T=0]
[B=1]
[R=1]
[CB=2]
[T=0]
[B=1]
[R=1]
[CB=2]
[T=0]
[B=1]
[R=1]
[CB=2]
[CT=3]
[N=1]
HEVC
10
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[CT=5]
[N=3]
[CT=0]
[N=0]
[CT=0]
[N=1]
[CT=0]
[N=2]
[CT=0]
[N=3]
[CT=1]
[N=0]
[CT=1]
[N=1]
[CT=1]
[N=2]
[CT=1]
[N=3]
[N=0]
[N=1]
[CT=2]
[N=2]
[CT=2]
[N=3]
[CT=3]
[N=0]
R29
ct_coef
[T=0]
[B=1]
[R=1]
[CB=2]
[CT=3]
[N=2]
[T=0]
[B=1]
[R=1]
[CB=2]
[CT=3]
[N=3]
[T=0]
[B=1]
[R=1]
[CB=2]
[CT=4]
[N=0]
[T=0]
[B=1]
[R=1]
[CB=2]
[CT=4]
[N=1]
[T=0]
[B=1]
[R=1]
[CB=2]
[CT=4]
[N=2]
[T=0]
[B=1]
[R=1]
[CB=2]
[CT=4]
[N=3]
[T=0]
[B=1]
[R=1]
[CB=2]
[CT=5]
[N=0]
[T=0]
[B=1]
[R=1]
[CB=2]
[CT=5]
[N=1]
[T=0]
[B=1]
[R=1]
[CB=2]
[CT=5]
[N=2]
[T=0]
[B=1]
[R=1]
[CB=2]
[CT=5]
[N=3]
[T=0]
[B=1]
[R=1]
[CB=3]
[CT=0]
[N=0]
[T=0]
[B=1]
[R=1]
[CB=3]
[CT=0]
[N=1]
[T=0]
[B=1]
[R=1]
[CB=3]
[CT=0]
[N=2]
[T=0]
[B=1]
[R=1]
[CB=3]
[CT=0]
[N=3]
[T=0]
[B=1]
[R=1]
[CB=3]
[CT=1]
[N=0]
[T=0]
[B=1]
[R=1]
[CB=3]
[CT=1]
[N=1]
R30
ct_coef
[T=0]
[B=1]
[R=1]
[CB=3]
[CT=1]
[N=2]
[T=0]
[B=1]
[R=1]
[CB=3]
[CT=1]
[N=3]
[T=0]
[B=1]
[R=1]
[CB=3]
[CT=2]
[N=0]
[T=0]
[B=1]
[R=1]
[CB=3]
[CT=2]
[N=1]
[T=0]
[B=1]
[R=1]
[CB=3]
[CT=2]
[N=2]
[T=0]
[B=1]
[R=1]
[CB=3]
[CT=2]
[N=3]
[T=0]
[B=1]
[R=1]
[CB=3]
[CT=3]
[N=0]
[T=0]
[B=1]
[R=1]
[CB=3]
[CT=3]
[N=1]
[T=0]
[B=1]
[R=1]
[CB=3]
[CT=3]
[N=2]
[T=0]
[B=1]
[R=1]
[CB=3]
[CT=3]
[N=3]
[T=0]
[B=1]
[R=1]
[CB=3]
[CT=4]
[N=0]
[T=0]
[B=1]
[R=1]
[CB=3]
[CT=4]
[N=1]
[T=0]
[B=1]
[R=1]
[CB=3]
[CT=4]
[N=2]
[T=0]
[B=1]
[R=1]
[CB=3]
[CT=4]
[N=3]
[T=0]
[B=1]
[R=1]
[CB=3]
[CT=5]
[N=0]
[T=0]
[B=1]
[R=1]
[CB=3]
[CT=5]
[N=1]
R31
ct_coef
[T=0]
[B=1]
[R=1]
[CB=3]
[CT=5]
[N=2]
[T=0]
[B=1]
[R=1]
[CB=3]
[CT=5]
[N=3]
[T=0]
[B=1]
[R=1]
[CB=4]
[CT=0]
[N=0]
[T=0]
[B=1]
[R=1]
[CB=4]
[CT=0]
[N=1]
[T=0]
[B=1]
[R=1]
[CB=4]
[CT=0]
[N=2]
[T=0]
[B=1]
[R=1]
[CB=4]
[CT=0]
[N=3]
[T=0]
[B=1]
[R=1]
[CB=4]
[CT=1]
[N=0]
[T=0]
[B=1]
[R=1]
[CB=4]
[CT=1]
[N=1]
[T=0]
[B=1]
[R=1]
[CB=4]
[CT=1]
[N=2]
[T=0]
[B=1]
[R=1]
[CB=4]
[CT=1]
[N=3]
[T=0]
[B=1]
[R=1]
[CB=4]
[CT=2]
[N=0]
[T=0]
[B=1]
[R=1]
[CB=4]
[CT=2]
[N=1]
[T=0]
[B=1]
[R=1]
[CB=4]
[CT=2]
[N=2]
[T=0]
[B=1]
[R=1]
[CB=4]
[CT=2]
[N=3]
[T=0]
[B=1]
[R=1]
[CB=4]
[CT=3]
[N=0]
[T=0]
[B=1]
[R=1]
[CB=4]
[CT=3]
[N=1]
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
11
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R32
ct_coef
[T=0]
[B=1]
[R=1]
[CB=4]
[CT=3]
[N=2]
[T=0]
[B=1]
[R=1]
[CB=4]
[CT=3]
[N=3]
[T=0]
[B=1]
[R=1]
[CB=4]
[CT=4]
[N=0]
[T=0]
[B=1]
[R=1]
[CB=4]
[CT=4]
[N=1]
[T=0]
[B=1]
[R=1]
[CB=4]
[CT=4]
[N=2]
[T=0]
[B=1]
[R=1]
[CB=4]
[CT=4]
[N=3]
[T=0]
[B=1]
[R=1]
[CB=4]
[CT=5]
[N=0]
[T=0]
[B=1]
[R=1]
[CB=4]
[CT=5]
[N=1]
[T=0]
[B=1]
[R=1]
[CB=4]
[CT=5]
[N=2]
[T=0]
[B=1]
[R=1]
[CB=4]
[CT=5]
[N=3]
[T=0]
[B=1]
[R=1]
[CB=5]
[CT=0]
[N=0]
[T=0]
[B=1]
[R=1]
[CB=5]
[CT=0]
[N=1]
[T=0]
[B=1]
[R=1]
[CB=5]
[CT=0]
[N=2]
[T=0]
[B=1]
[R=1]
[CB=5]
[CT=0]
[N=3]
[T=0]
[B=1]
[R=1]
[CB=5]
[CT=1]
[N=0]
[T=0]
[B=1]
[R=1]
[CB=5]
[CT=1]
[N=1]
R33
ct_coef
[T=0]
[B=1]
[R=1]
[CB=5]
[CT=1]
[N=2]
[T=0]
[B=1]
[R=1]
[CB=5]
[CT=1]
[N=3]
[T=0]
[B=1]
[R=1]
[CB=5]
[CT=2]
[N=0]
[T=0]
[B=1]
[R=1]
[CB=5]
[CT=2]
[N=1]
[T=0]
[B=1]
[R=1]
[CB=5]
[CT=2]
[N=2]
[T=0]
[B=1]
[R=1]
[CB=5]
[CT=2]
[N=3]
[T=0]
[B=1]
[R=1]
[CB=5]
[CT=3]
[N=0]
[T=0]
[B=1]
[R=1]
[CB=5]
[CT=3]
[N=1]
[T=0]
[B=1]
[R=1]
[CB=5]
[CT=3]
[N=2]
[T=0]
[B=1]
[R=1]
[CB=5]
[CT=3]
[N=3]
[T=0]
[B=1]
[R=1]
[CB=5]
[CT=4]
[N=0]
[T=0]
[B=1]
[R=1]
[CB=5]
[CT=4]
[N=1]
[T=0]
[B=1]
[R=1]
[CB=5]
[CT=4]
[N=2]
[T=0]
[B=1]
[R=1]
[CB=5]
[CT=4]
[N=3]
[T=0]
[B=1]
[R=1]
[CB=5]
[CT=5]
[N=0]
[T=0]
[B=1]
[R=1]
[CB=5]
[CT=5]
[N=1]
R34
ct_coef
[T=0]
[B=1]
[R=1]
[CB=5]
[CT=5]
[N=2]
[T=0]
[B=1]
[R=1]
[CB=5]
[CT=5]
[N=3]
[T=1]
[B=0]
[R=0]
[CB=0]
[CT=0]
[N=0]
[T=1]
[B=0]
[R=0]
[CB=0]
[CT=0]
[N=1]
[T=1]
[B=0]
[R=0]
[CB=0]
[CT=0]
[N=2]
[T=1]
[B=0]
[R=0]
[CB=0]
[CT=0]
[N=3]
[T=1]
[B=0]
[R=0]
[CB=0]
[CT=1]
[N=0]
[T=1]
[B=0]
[R=0]
[CB=0]
[CT=1]
[N=1]
[T=1]
[B=0]
[R=0]
[CB=0]
[CT=1]
[N=2]
[T=1]
[B=0]
[R=0]
[CB=0]
[CT=1]
[N=3]
[T=1]
[B=0]
[R=0]
[CB=0]
[CT=2]
[N=0]
[T=1]
[B=0]
[R=0]
[CB=0]
[CT=2]
[N=1]
[T=1]
[B=0]
[R=0]
[CB=0]
[CT=2]
[N=2]
[T=1]
[B=0]
[R=0]
[CB=0]
[CT=2]
[N=3]
[T=1]
[B=0]
[R=0]
[CB=1]
[CT=0]
[N=0]
[T=1]
[B=0]
[R=0]
[CB=1]
[CT=0]
[N=1]
R35
ct_coef
[T=1]
[T=1]
[T=1]
[T=1]
[T=1]
[T=1]
[T=1]
[T=1]
[T=1]
[T=1]
[T=1]
[T=1]
[T=1]
[T=1]
[T=1]
[T=1]
HEVC
12
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[B=0]
[R=0]
[CB=1]
[CT=0]
[N=2]
[B=0]
[R=0]
[CB=1]
[CT=0]
[N=3]
[B=0]
[R=0]
[CB=1]
[CT=1]
[N=0]
[B=0]
[R=0]
[CB=1]
[CT=1]
[N=1]
[B=0]
[R=0]
[CB=1]
[CT=1]
[N=2]
[B=0]
[R=0]
[CB=1]
[CT=1]
[N=3]
[B=0]
[R=0]
[CB=1]
[CT=2]
[N=0]
[B=0]
[R=0]
[CB=1]
[CT=2]
[N=1]
[B=0]
[R=0]
[CB=1]
[CT=2]
[N=2]
[B=0]
[R=0]
[CB=1]
[CT=2]
[N=3]
[B=0]
[R=0]
[CB=1]
[CT=3]
[N=0]
[B=0]
[R=0]
[CB=1]
[CT=3]
[N=1]
[B=0]
[R=0]
[CB=1]
[CT=3]
[N=2]
[B=0]
[R=0]
[CB=1]
[CT=3]
[N=3]
[B=0]
[R=0]
[CB=1]
[CT=4]
[N=0]
[B=0]
[R=0]
[CB=1]
[CT=4]
[N=1]
R36
ct_coef
[T=1]
[B=0]
[R=0]
[CB=1]
[CT=4]
[N=2]
[T=1]
[B=0]
[R=0]
[CB=1]
[CT=4]
[N=3]
[T=1]
[B=0]
[R=0]
[CB=1]
[CT=5]
[N=0]
[T=1]
[B=0]
[R=0]
[CB=1]
[CT=5]
[N=1]
[T=1]
[B=0]
[R=0]
[CB=1]
[CT=5]
[N=2]
[T=1]
[B=0]
[R=0]
[CB=1]
[CT=5]
[N=3]
[T=1]
[B=0]
[R=0]
[CB=2]
[CT=0]
[N=0]
[T=1]
[B=0]
[R=0]
[CB=2]
[CT=0]
[N=1]
[T=1]
[B=0]
[R=0]
[CB=2]
[CT=0]
[N=2]
[T=1]
[B=0]
[R=0]
[CB=2]
[CT=0]
[N=3]
[T=1]
[B=0]
[R=0]
[CB=2]
[CT=1]
[N=0]
[T=1]
[B=0]
[R=0]
[CB=2]
[CT=1]
[N=1]
[T=1]
[B=0]
[R=0]
[CB=2]
[CT=1]
[N=2]
[T=1]
[B=0]
[R=0]
[CB=2]
[CT=1]
[N=3]
[T=1]
[B=0]
[R=0]
[CB=2]
[CT=2]
[N=0]
[T=1]
[B=0]
[R=0]
[CB=2]
[CT=2]
[N=1]
R37
ct_coef
[T=1]
[B=0]
[R=0]
[CB=2]
[CT=2]
[N=2]
[T=1]
[B=0]
[R=0]
[CB=2]
[CT=2]
[N=3]
[T=1]
[B=0]
[R=0]
[CB=2]
[CT=3]
[N=0]
[T=1]
[B=0]
[R=0]
[CB=2]
[CT=3]
[N=1]
[T=1]
[B=0]
[R=0]
[CB=2]
[CT=3]
[N=2]
[T=1]
[B=0]
[R=0]
[CB=2]
[CT=3]
[N=3]
[T=1]
[B=0]
[R=0]
[CB=2]
[CT=4]
[N=0]
[T=1]
[B=0]
[R=0]
[CB=2]
[CT=4]
[N=1]
[T=1]
[B=0]
[R=0]
[CB=2]
[CT=4]
[N=2]
[T=1]
[B=0]
[R=0]
[CB=2]
[CT=4]
[N=3]
[T=1]
[B=0]
[R=0]
[CB=2]
[CT=5]
[N=0]
[T=1]
[B=0]
[R=0]
[CB=2]
[CT=5]
[N=1]
[T=1]
[B=0]
[R=0]
[CB=2]
[CT=5]
[N=2]
[T=1]
[B=0]
[R=0]
[CB=2]
[CT=5]
[N=3]
[T=1]
[B=0]
[R=0]
[CB=3]
[CT=0]
[N=0]
[T=1]
[B=0]
[R=0]
[CB=3]
[CT=0]
[N=1]
R38
ct_coef
[T=1]
[B=0]
[R=0]
[T=1]
[B=0]
[R=0]
[T=1]
[B=0]
[R=0]
[T=1]
[B=0]
[R=0]
[T=1]
[B=0]
[R=0]
[T=1]
[B=0]
[R=0]
[T=1]
[B=0]
[R=0]
[T=1]
[B=0]
[R=0]
[T=1]
[B=0]
[R=0]
[T=1]
[B=0]
[R=0]
[T=1]
[B=0]
[R=0]
[T=1]
[B=0]
[R=0]
[T=1]
[B=0]
[R=0]
[T=1]
[B=0]
[R=0]
[T=1]
[B=0]
[R=0]
[T=1]
[B=0]
[R=0]
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
13
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[CB=3]
[CT=0]
[N=2]
[CB=3]
[CT=0]
[N=3]
[CB=3]
[CT=1]
[N=0]
[CB=3]
[CT=1]
[N=1]
[CB=3]
[CT=1]
[N=2]
[CB=3]
[CT=1]
[N=3]
[CB=3]
[CT=2]
[N=0]
[CB=3]
[CT=2]
[N=1]
[CB=3]
[CT=2]
[N=2]
[CB=3]
[CT=2]
[N=3]
[CB=3]
[CT=3]
[N=0]
[CB=3]
[CT=3]
[N=1]
[CB=3]
[CT=3]
[N=2]
[CB=3]
[CT=3]
[N=3]
[CB=3]
[CT=4]
[N=0]
[CB=3]
[CT=4]
[N=1]
R39
ct_coef
[T=1]
[B=0]
[R=0]
[CB=3]
[CT=4]
[N=2]
[T=1]
[B=0]
[R=0]
[CB=3]
[CT=4]
[N=3]
[T=1]
[B=0]
[R=0]
[CB=3]
[CT=5]
[N=0]
[T=1]
[B=0]
[R=0]
[CB=3]
[CT=5]
[N=1]
[T=1]
[B=0]
[R=0]
[CB=3]
[CT=5]
[N=2]
[T=1]
[B=0]
[R=0]
[CB=3]
[CT=5]
[N=3]
[T=1]
[B=0]
[R=0]
[CB=4]
[CT=0]
[N=0]
[T=1]
[B=0]
[R=0]
[CB=4]
[CT=0]
[N=1]
[T=1]
[B=0]
[R=0]
[CB=4]
[CT=0]
[N=2]
[T=1]
[B=0]
[R=0]
[CB=4]
[CT=0]
[N=3]
[T=1]
[B=0]
[R=0]
[CB=4]
[CT=1]
[N=0]
[T=1]
[B=0]
[R=0]
[CB=4]
[CT=1]
[N=1]
[T=1]
[B=0]
[R=0]
[CB=4]
[CT=1]
[N=2]
[T=1]
[B=0]
[R=0]
[CB=4]
[CT=1]
[N=3]
[T=1]
[B=0]
[R=0]
[CB=4]
[CT=2]
[N=0]
[T=1]
[B=0]
[R=0]
[CB=4]
[CT=2]
[N=1]
R40
ct_coef
[T=1]
[B=0]
[R=0]
[CB=4]
[CT=2]
[N=2]
[T=1]
[B=0]
[R=0]
[CB=4]
[CT=2]
[N=3]
[T=1]
[B=0]
[R=0]
[CB=4]
[CT=3]
[N=0]
[T=1]
[B=0]
[R=0]
[CB=4]
[CT=3]
[N=1]
[T=1]
[B=0]
[R=0]
[CB=4]
[CT=3]
[N=2]
[T=1]
[B=0]
[R=0]
[CB=4]
[CT=3]
[N=3]
[T=1]
[B=0]
[R=0]
[CB=4]
[CT=4]
[N=0]
[T=1]
[B=0]
[R=0]
[CB=4]
[CT=4]
[N=1]
[T=1]
[B=0]
[R=0]
[CB=4]
[CT=4]
[N=2]
[T=1]
[B=0]
[R=0]
[CB=4]
[CT=4]
[N=3]
[T=1]
[B=0]
[R=0]
[CB=4]
[CT=5]
[N=0]
[T=1]
[B=0]
[R=0]
[CB=4]
[CT=5]
[N=1]
[T=1]
[B=0]
[R=0]
[CB=4]
[CT=5]
[N=2]
[T=1]
[B=0]
[R=0]
[CB=4]
[CT=5]
[N=3]
[T=1]
[B=0]
[R=0]
[CB=5]
[CT=0]
[N=0]
[T=1]
[B=0]
[R=0]
[CB=5]
[CT=0]
[N=1]
R41
ct_coef
[T=1]
[B=0]
[R=0]
[CB=5]
[CT=0]
[T=1]
[B=0]
[R=0]
[CB=5]
[T=1]
[B=0]
[R=0]
[CB=5]
[T=1]
[B=0]
[R=0]
[CB=5]
[T=1]
[B=0]
[R=0]
[CB=5]
[T=1]
[B=0]
[R=0]
[CB=5]
[T=1]
[B=0]
[R=0]
[CB=5]
[T=1]
[B=0]
[R=0]
[CB=5]
[T=1]
[B=0]
[R=0]
[CB=5]
[T=1]
[B=0]
[R=0]
[CB=5]
[T=1]
[B=0]
[R=0]
[CB=5]
[T=1]
[B=0]
[R=0]
[CB=5]
[T=1]
[B=0]
[R=0]
[CB=5]
[T=1]
[B=0]
[R=0]
[CB=5]
[T=1]
[B=0]
[R=0]
[CB=5]
[T=1]
[B=0]
[R=0]
[CB=5]
[CT=4]
HEVC
14
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[N=2]
[CT=0]
[N=3]
[CT=1]
[N=0]
[CT=1]
[N=1]
[CT=1]
[N=2]
[CT=1]
[N=3]
[CT=2]
[N=0]
[CT=2]
[N=1]
[CT=2]
[N=2]
[CT=2]
[N=3]
[CT=3]
[N=0]
[CT=3]
[N=1]
[CT=3]
[N=2]
[CT=3]
[N=3]
[CT=4]
[N=0]
[N=1]
R42
ct_coef
[T=1]
[B=0]
[R=0]
[CB=5]
[CT=4]
[N=2]
[T=1]
[B=0]
[R=0]
[CB=5]
[CT=4]
[N=3]
[T=1]
[B=0]
[R=0]
[CB=5]
[CT=5]
[N=0]
[T=1]
[B=0]
[R=0]
[CB=5]
[CT=5]
[N=1]
[T=1]
[B=0]
[R=0]
[CB=5]
[CT=5]
[N=2]
[T=1]
[B=0]
[R=0]
[CB=5]
[CT=5]
[N=3]
[T=1]
[B=0]
[R=1]
[CB=0]
[CT=0]
[N=0]
[T=1]
[B=0]
[R=1]
[CB=0]
[CT=0]
[N=1]
[T=1]
[B=0]
[R=1]
[CB=0]
[CT=0]
[N=2]
[T=1]
[B=0]
[R=1]
[CB=0]
[CT=0]
[N=3]
[T=1]
[B=0]
[R=1]
[CB=0]
[CT=1]
[N=0]
[T=1]
[B=0]
[R=1]
[CB=0]
[CT=1]
[N=1]
[T=1]
[B=0]
[R=1]
[CB=0]
[CT=1]
[N=2]
[T=1]
[B=0]
[R=1]
[CB=0]
[CT=1]
[N=3]
[T=1]
[B=0]
[R=1]
[CB=0]
[CT=2]
[N=0]
[T=1]
[B=0]
[R=1]
[CB=0]
[CT=2]
[N=1]
R43
ct_coef
[T=1]
[B=0]
[R=1]
[CB=0]
[CT=2]
[N=2]
[T=1]
[B=0]
[R=1]
[CB=0]
[CT=2]
[N=3]
[T=1]
[B=0]
[R=1]
[CB=1]
[CT=0]
[N=0]
[T=1]
[B=0]
[R=1]
[CB=1]
[CT=0]
[N=1]
[T=1]
[B=0]
[R=1]
[CB=1]
[CT=0]
[N=2]
[T=1]
[B=0]
[R=1]
[CB=1]
[CT=0]
[N=3]
[T=1]
[B=0]
[R=1]
[CB=1]
[CT=1]
[N=0]
[T=1]
[B=0]
[R=1]
[CB=1]
[CT=1]
[N=1]
[T=1]
[B=0]
[R=1]
[CB=1]
[CT=1]
[N=2]
[T=1]
[B=0]
[R=1]
[CB=1]
[CT=1]
[N=3]
[T=1]
[B=0]
[R=1]
[CB=1]
[CT=2]
[N=0]
[T=1]
[B=0]
[R=1]
[CB=1]
[CT=2]
[N=1]
[T=1]
[B=0]
[R=1]
[CB=1]
[CT=2]
[N=2]
[T=1]
[B=0]
[R=1]
[CB=1]
[CT=2]
[N=3]
[T=1]
[B=0]
[R=1]
[CB=1]
[CT=3]
[N=0]
[T=1]
[B=0]
[R=1]
[CB=1]
[CT=3]
[N=1]
R44
ct_coef
[T=1]
[B=0]
[R=1]
[CB=1]
[CT=3]
[N=2]
[T=1]
[B=0]
[R=1]
[CB=1]
[CT=3]
[T=1]
[B=0]
[R=1]
[CB=1]
[CT=4]
[T=1]
[B=0]
[R=1]
[CB=1]
[CT=4]
[T=1]
[B=0]
[R=1]
[CB=1]
[CT=4]
[T=1]
[B=0]
[R=1]
[CB=1]
[CT=4]
[T=1]
[B=0]
[R=1]
[CB=1]
[CT=5]
[T=1]
[B=0]
[R=1]
[CB=1]
[CT=5]
[T=1]
[B=0]
[R=1]
[CB=1]
[CT=5]
[T=1]
[B=0]
[R=1]
[CB=1]
[CT=5]
[T=1]
[B=0]
[R=1]
[CB=2]
[CT=0]
[N=0]
[T=1]
[B=0]
[R=1]
[CB=2]
[CT=0]
[N=1]
[T=1]
[B=0]
[R=1]
[CB=2]
[CT=0]
[T=1]
[B=0]
[R=1]
[CB=2]
[CT=0]
[T=1]
[B=0]
[R=1]
[CB=2]
[CT=1]
[T=1]
[B=0]
[R=1]
[CB=2]
[CT=1]
[N=1]
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
15
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[N=3]
[N=0]
[N=1]
[N=2]
[N=3]
[N=0]
[N=1]
[N=2]
[N=3]
[N=2]
[N=3]
[N=0]
R45
ct_coef
[T=1]
[B=0]
[R=1]
[CB=2]
[CT=1]
[N=2]
[T=1]
[B=0]
[R=1]
[CB=2]
[CT=1]
[N=3]
[T=1]
[B=0]
[R=1]
[CB=2]
[CT=2]
[N=0]
[T=1]
[B=0]
[R=1]
[CB=2]
[CT=2]
[N=1]
[T=1]
[B=0]
[R=1]
[CB=2]
[CT=2]
[N=2]
[T=1]
[B=0]
[R=1]
[CB=2]
[CT=2]
[N=3]
[T=1]
[B=0]
[R=1]
[CB=2]
[CT=3]
[N=0]
[T=1]
[B=0]
[R=1]
[CB=2]
[CT=3]
[N=1]
[T=1]
[B=0]
[R=1]
[CB=2]
[CT=3]
[N=2]
[T=1]
[B=0]
[R=1]
[CB=2]
[CT=3]
[N=3]
[T=1]
[B=0]
[R=1]
[CB=2]
[CT=4]
[N=0]
[T=1]
[B=0]
[R=1]
[CB=2]
[CT=4]
[N=1]
[T=1]
[B=0]
[R=1]
[CB=2]
[CT=4]
[N=2]
[T=1]
[B=0]
[R=1]
[CB=2]
[CT=4]
[N=3]
[T=1]
[B=0]
[R=1]
[CB=2]
[CT=5]
[N=0]
[T=1]
[B=0]
[R=1]
[CB=2]
[CT=5]
[N=1]
R46
ct_coef
[T=1]
[B=0]
[R=1]
[CB=2]
[CT=5]
[N=2]
[T=1]
[B=0]
[R=1]
[CB=2]
[CT=5]
[N=3]
[T=1]
[B=0]
[R=1]
[CB=3]
[CT=0]
[N=0]
[T=1]
[B=0]
[R=1]
[CB=3]
[CT=0]
[N=1]
[T=1]
[B=0]
[R=1]
[CB=3]
[CT=0]
[N=2]
[T=1]
[B=0]
[R=1]
[CB=3]
[CT=0]
[N=3]
[T=1]
[B=0]
[R=1]
[CB=3]
[CT=1]
[N=0]
[T=1]
[B=0]
[R=1]
[CB=3]
[CT=1]
[N=1]
[T=1]
[B=0]
[R=1]
[CB=3]
[CT=1]
[N=2]
[T=1]
[B=0]
[R=1]
[CB=3]
[CT=1]
[N=3]
[T=1]
[B=0]
[R=1]
[CB=3]
[CT=2]
[N=0]
[T=1]
[B=0]
[R=1]
[CB=3]
[CT=2]
[N=1]
[T=1]
[B=0]
[R=1]
[CB=3]
[CT=2]
[N=2]
[T=1]
[B=0]
[R=1]
[CB=3]
[CT=2]
[N=3]
[T=1]
[B=0]
[R=1]
[CB=3]
[CT=3]
[N=0]
[T=1]
[B=0]
[R=1]
[CB=3]
[CT=3]
[N=1]
R47
ct_coef
[T=1]
[B=0]
[R=1]
[CB=3]
[CT=3]
[N=2]
[T=1]
[B=0]
[R=1]
[CB=3]
[CT=3]
[N=3]
[T=1]
[B=0]
[R=1]
[CB=3]
[CT=4]
[N=0]
[T=1]
[B=0]
[R=1]
[CB=3]
[CT=4]
[N=1]
[T=1]
[B=0]
[R=1]
[CB=3]
[CT=4]
[N=2]
[T=1]
[B=0]
[R=1]
[CB=3]
[CT=4]
[N=3]
[T=1]
[B=0]
[R=1]
[CB=3]
[CT=5]
[N=0]
[T=1]
[B=0]
[R=1]
[CB=3]
[CT=5]
[N=1]
[T=1]
[B=0]
[R=1]
[CB=3]
[CT=5]
[N=2]
[T=1]
[B=0]
[R=1]
[CB=3]
[CT=5]
[N=3]
[T=1]
[B=0]
[R=1]
[CB=4]
[CT=0]
[N=0]
[T=1]
[B=0]
[R=1]
[CB=4]
[CT=0]
[N=1]
[T=1]
[B=0]
[R=1]
[CB=4]
[CT=0]
[N=2]
[T=1]
[B=0]
[R=1]
[CB=4]
[CT=0]
[N=3]
[T=1]
[B=0]
[R=1]
[CB=4]
[CT=1]
[N=0]
[T=1]
[B=0]
[R=1]
[CB=4]
[CT=1]
[N=1]
R48
ct_coef
HEVC
16
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[T=1]
[B=0]
[R=1]
[CB=4]
[CT=1]
[N=2]
[T=1]
[B=0]
[R=1]
[CB=4]
[CT=1]
[N=3]
[T=1]
[B=0]
[R=1]
[CB=4]
[CT=2]
[N=0]
[T=1]
[B=0]
[R=1]
[CB=4]
[CT=2]
[N=1]
[T=1]
[B=0]
[R=1]
[CB=4]
[CT=2]
[N=2]
[T=1]
[B=0]
[R=1]
[CB=4]
[CT=2]
[N=3]
[T=1]
[B=0]
[R=1]
[CB=4]
[CT=3]
[N=0]
[T=1]
[B=0]
[R=1]
[CB=4]
[CT=3]
[N=1]
[T=1]
[B=0]
[R=1]
[CB=4]
[CT=3]
[N=2]
[T=1]
[B=0]
[R=1]
[CB=4]
[CT=3]
[N=3]
[T=1]
[B=0]
[R=1]
[CB=4]
[CT=4]
[N=0]
[T=1]
[B=0]
[R=1]
[CB=4]
[CT=4]
[N=1]
[T=1]
[B=0]
[R=1]
[CB=4]
[CT=4]
[N=2]
[T=1]
[B=0]
[R=1]
[CB=4]
[CT=4]
[N=3]
[T=1]
[B=0]
[R=1]
[CB=4]
[CT=5]
[N=0]
[T=1]
[B=0]
[R=1]
[CB=4]
[CT=5]
[N=1]
R49
ct_coef
[T=1]
[B=0]
[R=1]
[CB=4]
[CT=5]
[N=2]
[T=1]
[B=0]
[R=1]
[CB=4]
[CT=5]
[N=3]
[T=1]
[B=0]
[R=1]
[CB=5]
[CT=0]
[N=0]
[T=1]
[B=0]
[R=1]
[CB=5]
[CT=0]
[N=1]
[T=1]
[B=0]
[R=1]
[CB=5]
[CT=0]
[N=2]
[T=1]
[B=0]
[R=1]
[CB=5]
[CT=0]
[N=3]
[T=1]
[B=0]
[R=1]
[CB=5]
[CT=1]
[N=0]
[T=1]
[B=0]
[R=1]
[CB=5]
[CT=1]
[N=1]
[T=1]
[B=0]
[R=1]
[CB=5]
[CT=1]
[N=2]
[T=1]
[B=0]
[R=1]
[CB=5]
[CT=1]
[N=3]
[T=1]
[B=0]
[R=1]
[CB=5]
[CT=2]
[N=0]
[T=1]
[B=0]
[R=1]
[CB=5]
[CT=2]
[N=1]
[T=1]
[B=0]
[R=1]
[CB=5]
[CT=2]
[N=2]
[T=1]
[B=0]
[R=1]
[CB=5]
[CT=2]
[N=3]
[T=1]
[B=0]
[R=1]
[CB=5]
[CT=3]
[N=0]
[T=1]
[B=0]
[R=1]
[CB=5]
[CT=3]
[N=1]
R50
ct_coef
[T=1]
[B=0]
[R=1]
[CB=5]
[CT=3]
[N=2]
[T=1]
[B=0]
[R=1]
[CB=5]
[CT=3]
[N=3]
[T=1]
[B=0]
[R=1]
[CB=5]
[CT=4]
[N=0]
[T=1]
[B=0]
[R=1]
[CB=5]
[CT=4]
[N=1]
[T=1]
[B=0]
[R=1]
[CB=5]
[CT=4]
[N=2]
[T=1]
[B=0]
[R=1]
[CB=5]
[CT=4]
[N=3]
[T=1]
[B=0]
[R=1]
[CB=5]
[CT=5]
[N=0]
[T=1]
[B=0]
[R=1]
[CB=5]
[CT=5]
[N=1]
[T=1]
[B=0]
[R=1]
[CB=5]
[CT=5]
[N=2]
[T=1]
[B=0]
[R=1]
[CB=5]
[CT=5]
[N=3]
[T=1]
[B=1]
[R=0]
[CB=0]
[CT=0]
[N=0]
[T=1]
[B=1]
[R=0]
[CB=0]
[CT=0]
[N=1]
[T=1]
[B=1]
[R=0]
[CB=0]
[CT=0]
[N=2]
[T=1]
[B=1]
[R=0]
[CB=0]
[CT=0]
[N=3]
[T=1]
[B=1]
[R=0]
[CB=0]
[CT=1]
[N=0]
[T=1]
[B=1]
[R=0]
[CB=0]
[CT=1]
[N=1]
R51
ct_coef
[T=1]
[B=1]
[T=1]
[B=1]
[T=1]
[B=1]
[T=1]
[B=1]
[T=1]
[B=1]
[T=1]
[B=1]
[T=1]
[B=1]
[T=1]
[B=1]
[T=1]
[B=1]
[T=1]
[B=1]
[T=1]
[B=1]
[T=1]
[B=1]
[T=1]
[B=1]
[T=1]
[B=1]
[T=1]
[B=1]
[T=1]
[B=1]
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
17
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[R=0]
[CB=0]
[CT=1]
[N=2]
[R=0]
[CB=0]
[CT=1]
[N=3]
[R=0]
[CB=0]
[CT=2]
[N=0]
[R=0]
[CB=0]
[CT=2]
[N=1]
[R=0]
[CB=0]
[CT=2]
[N=2]
[R=0]
[CB=0]
[CT=2]
[N=3]
[R=0]
[CB=1]
[CT=0]
[N=0]
[R=0]
[CB=1]
[CT=0]
[N=1]
[R=0]
[CB=1]
[CT=0]
[N=2]
[R=0]
[CB=1]
[CT=0]
[N=3]
[R=0]
[CB=1]
[CT=1]
[N=0]
[R=0]
[CB=1]
[CT=1]
[N=1]
[R=0]
[CB=1]
[CT=1]
[N=2]
[R=0]
[CB=1]
[CT=1]
[N=3]
[R=0]
[CB=1]
[CT=2]
[N=0]
[R=0]
[CB=1]
[CT=2]
[N=1]
R52
ct_coef
[T=1]
[B=1]
[R=0]
[CB=1]
[CT=2]
[N=2]
[T=1]
[B=1]
[R=0]
[CB=1]
[CT=2]
[N=3]
[T=1]
[B=1]
[R=0]
[CB=1]
[CT=3]
[N=0]
[T=1]
[B=1]
[R=0]
[CB=1]
[CT=3]
[N=1]
[T=1]
[B=1]
[R=0]
[CB=1]
[CT=3]
[N=2]
[T=1]
[B=1]
[R=0]
[CB=1]
[CT=3]
[N=3]
[T=1]
[B=1]
[R=0]
[CB=1]
[CT=4]
[N=0]
[T=1]
[B=1]
[R=0]
[CB=1]
[CT=4]
[N=1]
[T=1]
[B=1]
[R=0]
[CB=1]
[CT=4]
[N=2]
[T=1]
[B=1]
[R=0]
[CB=1]
[CT=4]
[N=3]
[T=1]
[B=1]
[R=0]
[CB=1]
[CT=5]
[N=0]
[T=1]
[B=1]
[R=0]
[CB=1]
[CT=5]
[N=1]
[T=1]
[B=1]
[R=0]
[CB=1]
[CT=5]
[N=2]
[T=1]
[B=1]
[R=0]
[CB=1]
[CT=5]
[N=3]
[T=1]
[B=1]
[R=0]
[CB=2]
[CT=0]
[N=0]
[T=1]
[B=1]
[R=0]
[CB=2]
[CT=0]
[N=1]
R53
ct_coef
[T=1]
[B=1]
[R=0]
[CB=2]
[CT=0]
[N=2]
[T=1]
[B=1]
[R=0]
[CB=2]
[CT=0]
[N=3]
[T=1]
[B=1]
[R=0]
[CB=2]
[CT=1]
[N=0]
[T=1]
[B=1]
[R=0]
[CB=2]
[CT=1]
[N=1]
[T=1]
[B=1]
[R=0]
[CB=2]
[CT=1]
[N=2]
[T=1]
[B=1]
[R=0]
[CB=2]
[CT=1]
[N=3]
[T=1]
[B=1]
[R=0]
[CB=2]
[CT=2]
[N=0]
[T=1]
[B=1]
[R=0]
[CB=2]
[CT=2]
[N=1]
[T=1]
[B=1]
[R=0]
[CB=2]
[CT=2]
[N=2]
[T=1]
[B=1]
[R=0]
[CB=2]
[CT=2]
[N=3]
[T=1]
[B=1]
[R=0]
[CB=2]
[CT=3]
[N=0]
[T=1]
[B=1]
[R=0]
[CB=2]
[CT=3]
[N=1]
[T=1]
[B=1]
[R=0]
[CB=2]
[CT=3]
[N=2]
[T=1]
[B=1]
[R=0]
[CB=2]
[CT=3]
[N=3]
[T=1]
[B=1]
[R=0]
[CB=2]
[CT=4]
[N=0]
[T=1]
[B=1]
[R=0]
[CB=2]
[CT=4]
[N=1]
R54
ct_coef
[T=1]
[B=1]
[R=0]
[CB=2]
[T=1]
[B=1]
[R=0]
[T=1]
[B=1]
[R=0]
[T=1]
[B=1]
[R=0]
[T=1]
[B=1]
[R=0]
[T=1]
[B=1]
[R=0]
[T=1]
[B=1]
[R=0]
[T=1]
[B=1]
[R=0]
[T=1]
[B=1]
[R=0]
[T=1]
[B=1]
[R=0]
[T=1]
[B=1]
[R=0]
[T=1]
[B=1]
[R=0]
[T=1]
[B=1]
[R=0]
[T=1]
[B=1]
[R=0]
[T=1]
[B=1]
[R=0]
[T=1]
[B=1]
[R=0]
[CB=3]
HEVC
18
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[CT=4]
[N=2]
[CB=2]
[CT=4]
[N=3]
[CB=2]
[CT=5]
[N=0]
[CB=2]
[CT=5]
[N=1]
[CB=2]
[CT=5]
[N=2]
[CB=2]
[CT=5]
[N=3]
[CB=3]
[CT=0]
[N=0]
[CB=3]
[CT=0]
[N=1]
[CB=3]
[CT=0]
[N=2]
[CB=3]
[CT=0]
[N=3]
[CB=3]
[CT=1]
[N=0]
[CB=3]
[CT=1]
[N=1]
[CB=3]
[CT=1]
[N=2]
[CB=3]
[CT=1]
[N=3]
[CB=3]
[CT=2]
[N=0]
[CT=2]
[N=1]
R55
ct_coef
[T=1]
[B=1]
[R=0]
[CB=3]
[CT=2]
[N=2]
[T=1]
[B=1]
[R=0]
[CB=3]
[CT=2]
[N=3]
[T=1]
[B=1]
[R=0]
[CB=3]
[CT=3]
[N=0]
[T=1]
[B=1]
[R=0]
[CB=3]
[CT=3]
[N=1]
[T=1]
[B=1]
[R=0]
[CB=3]
[CT=3]
[N=2]
[T=1]
[B=1]
[R=0]
[CB=3]
[CT=3]
[N=3]
[T=1]
[B=1]
[R=0]
[CB=3]
[CT=4]
[N=0]
[T=1]
[B=1]
[R=0]
[CB=3]
[CT=4]
[N=1]
[T=1]
[B=1]
[R=0]
[CB=3]
[CT=4]
[N=2]
[T=1]
[B=1]
[R=0]
[CB=3]
[CT=4]
[N=3]
[T=1]
[B=1]
[R=0]
[CB=3]
[CT=5]
[N=0]
[T=1]
[B=1]
[R=0]
[CB=3]
[CT=5]
[N=1]
[T=1]
[B=1]
[R=0]
[CB=3]
[CT=5]
[N=2]
[T=1]
[B=1]
[R=0]
[CB=3]
[CT=5]
[N=3]
[T=1]
[B=1]
[R=0]
[CB=4]
[CT=0]
[N=0]
[T=1]
[B=1]
[R=0]
[CB=4]
[CT=0]
[N=1]
R56
ct_coef
[T=1]
[B=1]
[R=0]
[CB=4]
[CT=0]
[N=2]
[T=1]
[B=1]
[R=0]
[CB=4]
[CT=0]
[N=3]
[T=1]
[B=1]
[R=0]
[CB=4]
[CT=1]
[N=0]
[T=1]
[B=1]
[R=0]
[CB=4]
[CT=1]
[N=1]
[T=1]
[B=1]
[R=0]
[CB=4]
[CT=1]
[N=2]
[T=1]
[B=1]
[R=0]
[CB=4]
[CT=1]
[N=3]
[T=1]
[B=1]
[R=0]
[CB=4]
[CT=2]
[N=0]
[T=1]
[B=1]
[R=0]
[CB=4]
[CT=2]
[N=1]
[T=1]
[B=1]
[R=0]
[CB=4]
[CT=2]
[N=2]
[T=1]
[B=1]
[R=0]
[CB=4]
[CT=2]
[N=3]
[T=1]
[B=1]
[R=0]
[CB=4]
[CT=3]
[N=0]
[T=1]
[B=1]
[R=0]
[CB=4]
[CT=3]
[N=1]
[T=1]
[B=1]
[R=0]
[CB=4]
[CT=3]
[N=2]
[T=1]
[B=1]
[R=0]
[CB=4]
[CT=3]
[N=3]
[T=1]
[B=1]
[R=0]
[CB=4]
[CT=4]
[N=0]
[T=1]
[B=1]
[R=0]
[CB=4]
[CT=4]
[N=1]
R57
ct_coef
[T=1]
[B=1]
[R=0]
[CB=4]
[CT=4]
[N=2]
[T=1]
[B=1]
[R=0]
[CB=4]
[T=1]
[B=1]
[R=0]
[CB=4]
[T=1]
[B=1]
[R=0]
[CB=4]
[T=1]
[B=1]
[R=0]
[CB=4]
[T=1]
[B=1]
[R=0]
[CB=4]
[T=1]
[B=1]
[R=0]
[CB=5]
[T=1]
[B=1]
[R=0]
[CB=5]
[T=1]
[B=1]
[R=0]
[CB=5]
[T=1]
[B=1]
[R=0]
[CB=5]
[T=1]
[B=1]
[R=0]
[CB=5]
[CT=1]
[T=1]
[B=1]
[R=0]
[CB=5]
[CT=1]
[T=1]
[B=1]
[R=0]
[CB=5]
[T=1]
[B=1]
[R=0]
[CB=5]
[T=1]
[B=1]
[R=0]
[CB=5]
[T=1]
[B=1]
[R=0]
[CB=5]
[CT=2]
[N=1]
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
19
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[CT=4]
[N=3]
[CT=5]
[N=0]
[CT=5]
[N=1]
[CT=5]
[N=2]
[CT=5]
[N=3]
[CT=0]
[N=0]
[CT=0]
[N=1]
[CT=0]
[N=2]
[CT=0]
[N=3]
[N=0]
[N=1]
[CT=1]
[N=2]
[CT=1]
[N=3]
[CT=2]
[N=0]
R58
ct_coef
[T=1]
[B=1]
[R=0]
[CB=5]
[CT=2]
[N=2]
[T=1]
[B=1]
[R=0]
[CB=5]
[CT=2]
[N=3]
[T=1]
[B=1]
[R=0]
[CB=5]
[CT=3]
[N=0]
[T=1]
[B=1]
[R=0]
[CB=5]
[CT=3]
[N=1]
[T=1]
[B=1]
[R=0]
[CB=5]
[CT=3]
[N=2]
[T=1]
[B=1]
[R=0]
[CB=5]
[CT=3]
[N=3]
[T=1]
[B=1]
[R=0]
[CB=5]
[CT=4]
[N=0]
[T=1]
[B=1]
[R=0]
[CB=5]
[CT=4]
[N=1]
[T=1]
[B=1]
[R=0]
[CB=5]
[CT=4]
[N=2]
[T=1]
[B=1]
[R=0]
[CB=5]
[CT=4]
[N=3]
[T=1]
[B=1]
[R=0]
[CB=5]
[CT=5]
[N=0]
[T=1]
[B=1]
[R=0]
[CB=5]
[CT=5]
[N=1]
[T=1]
[B=1]
[R=0]
[CB=5]
[CT=5]
[N=2]
[T=1]
[B=1]
[R=0]
[CB=5]
[CT=5]
[N=3]
[T=1]
[B=1]
[R=1]
[CB=0]
[CT=0]
[N=0]
[T=1]
[B=1]
[R=1]
[CB=0]
[CT=0]
[N=1]
R59
ct_coef
[T=1]
[B=1]
[R=1]
[CB=0]
[CT=0]
[N=2]
[T=1]
[B=1]
[R=1]
[CB=0]
[CT=0]
[N=3]
[T=1]
[B=1]
[R=1]
[CB=0]
[CT=1]
[N=0]
[T=1]
[B=1]
[R=1]
[CB=0]
[CT=1]
[N=1]
[T=1]
[B=1]
[R=1]
[CB=0]
[CT=1]
[N=2]
[T=1]
[B=1]
[R=1]
[CB=0]
[CT=1]
[N=3]
[T=1]
[B=1]
[R=1]
[CB=0]
[CT=2]
[N=0]
[T=1]
[B=1]
[R=1]
[CB=0]
[CT=2]
[N=1]
[T=1]
[B=1]
[R=1]
[CB=0]
[CT=2]
[N=2]
[T=1]
[B=1]
[R=1]
[CB=0]
[CT=2]
[N=3]
[T=1]
[B=1]
[R=1]
[CB=1]
[CT=0]
[N=0]
[T=1]
[B=1]
[R=1]
[CB=1]
[CT=0]
[N=1]
[T=1]
[B=1]
[R=1]
[CB=1]
[CT=0]
[N=2]
[T=1]
[B=1]
[R=1]
[CB=1]
[CT=0]
[N=3]
[T=1]
[B=1]
[R=1]
[CB=1]
[CT=1]
[N=0]
[T=1]
[B=1]
[R=1]
[CB=1]
[CT=1]
[N=1]
R60
ct_coef
[T=1]
[B=1]
[R=1]
[CB=1]
[CT=1]
[N=2]
[T=1]
[B=1]
[R=1]
[CB=1]
[CT=1]
[N=3]
[T=1]
[B=1]
[R=1]
[CB=1]
[CT=2]
[N=0]
[T=1]
[B=1]
[R=1]
[CB=1]
[CT=2]
[N=1]
[T=1]
[B=1]
[R=1]
[CB=1]
[CT=2]
[N=2]
[T=1]
[B=1]
[R=1]
[CB=1]
[CT=2]
[N=3]
[T=1]
[B=1]
[R=1]
[CB=1]
[CT=3]
[N=0]
[T=1]
[B=1]
[R=1]
[CB=1]
[CT=3]
[N=1]
[T=1]
[B=1]
[R=1]
[CB=1]
[CT=3]
[N=2]
[T=1]
[B=1]
[R=1]
[CB=1]
[CT=3]
[N=3]
[T=1]
[B=1]
[R=1]
[CB=1]
[CT=4]
[N=0]
[T=1]
[B=1]
[R=1]
[CB=1]
[CT=4]
[N=1]
[T=1]
[B=1]
[R=1]
[CB=1]
[CT=4]
[N=2]
[T=1]
[B=1]
[R=1]
[CB=1]
[CT=4]
[N=3]
[T=1]
[B=1]
[R=1]
[CB=1]
[CT=5]
[N=0]
[T=1]
[B=1]
[R=1]
[CB=1]
[CT=5]
[N=1]
HEVC
20
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R61
ct_coef
[T=1]
[B=1]
[R=1]
[CB=1]
[CT=5]
[N=2]
[T=1]
[B=1]
[R=1]
[CB=1]
[CT=5]
[N=3]
[T=1]
[B=1]
[R=1]
[CB=2]
[CT=0]
[N=0]
[T=1]
[B=1]
[R=1]
[CB=2]
[CT=0]
[N=1]
[T=1]
[B=1]
[R=1]
[CB=2]
[CT=0]
[N=2]
[T=1]
[B=1]
[R=1]
[CB=2]
[CT=0]
[N=3]
[T=1]
[B=1]
[R=1]
[CB=2]
[CT=1]
[N=0]
[T=1]
[B=1]
[R=1]
[CB=2]
[CT=1]
[N=1]
[T=1]
[B=1]
[R=1]
[CB=2]
[CT=1]
[N=2]
[T=1]
[B=1]
[R=1]
[CB=2]
[CT=1]
[N=3]
[T=1]
[B=1]
[R=1]
[CB=2]
[CT=2]
[N=0]
[T=1]
[B=1]
[R=1]
[CB=2]
[CT=2]
[N=1]
[T=1]
[B=1]
[R=1]
[CB=2]
[CT=2]
[N=2]
[T=1]
[B=1]
[R=1]
[CB=2]
[CT=2]
[N=3]
[T=1]
[B=1]
[R=1]
[CB=2]
[CT=3]
[N=0]
[T=1]
[B=1]
[R=1]
[CB=2]
[CT=3]
[N=1]
R62
ct_coef
[T=1]
[B=1]
[R=1]
[CB=2]
[CT=3]
[N=2]
[T=1]
[B=1]
[R=1]
[CB=2]
[CT=3]
[N=3]
[T=1]
[B=1]
[R=1]
[CB=2]
[CT=4]
[N=0]
[T=1]
[B=1]
[R=1]
[CB=2]
[CT=4]
[N=1]
[T=1]
[B=1]
[R=1]
[CB=2]
[CT=4]
[N=2]
[T=1]
[B=1]
[R=1]
[CB=2]
[CT=4]
[N=3]
[T=1]
[B=1]
[R=1]
[CB=2]
[CT=5]
[N=0]
[T=1]
[B=1]
[R=1]
[CB=2]
[CT=5]
[N=1]
[T=1]
[B=1]
[R=1]
[CB=2]
[CT=5]
[N=2]
[T=1]
[B=1]
[R=1]
[CB=2]
[CT=5]
[N=3]
[T=1]
[B=1]
[R=1]
[CB=3]
[CT=0]
[N=0]
[T=1]
[B=1]
[R=1]
[CB=3]
[CT=0]
[N=1]
[T=1]
[B=1]
[R=1]
[CB=3]
[CT=0]
[N=2]
[T=1]
[B=1]
[R=1]
[CB=3]
[CT=0]
[N=3]
[T=1]
[B=1]
[R=1]
[CB=3]
[CT=1]
[N=0]
[T=1]
[B=1]
[R=1]
[CB=3]
[CT=1]
[N=1]
R63
ct_coef
[T=1]
[B=1]
[R=1]
[CB=3]
[CT=1]
[N=2]
[T=1]
[B=1]
[R=1]
[CB=3]
[CT=1]
[N=3]
[T=1]
[B=1]
[R=1]
[CB=3]
[CT=2]
[N=0]
[T=1]
[B=1]
[R=1]
[CB=3]
[CT=2]
[N=1]
[T=1]
[B=1]
[R=1]
[CB=3]
[CT=2]
[N=2]
[T=1]
[B=1]
[R=1]
[CB=3]
[CT=2]
[N=3]
[T=1]
[B=1]
[R=1]
[CB=3]
[CT=3]
[N=0]
[T=1]
[B=1]
[R=1]
[CB=3]
[CT=3]
[N=1]
[T=1]
[B=1]
[R=1]
[CB=3]
[CT=3]
[N=2]
[T=1]
[B=1]
[R=1]
[CB=3]
[CT=3]
[N=3]
[T=1]
[B=1]
[R=1]
[CB=3]
[CT=4]
[N=0]
[T=1]
[B=1]
[R=1]
[CB=3]
[CT=4]
[N=1]
[T=1]
[B=1]
[R=1]
[CB=3]
[CT=4]
[N=2]
[T=1]
[B=1]
[R=1]
[CB=3]
[CT=4]
[N=3]
[T=1]
[B=1]
[R=1]
[CB=3]
[CT=5]
[N=0]
[T=1]
[B=1]
[R=1]
[CB=3]
[CT=5]
[N=1]
R64
ct_coef
[T=1]
[T=1]
[T=1]
[T=1]
[T=1]
[T=1]
[T=1]
[T=1]
[T=1]
[T=1]
[T=1]
[T=1]
[T=1]
[T=1]
[T=1]
[T=1]
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
21
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[B=1]
[R=1]
[CB=3]
[CT=5]
[N=2]
[B=1]
[R=1]
[CB=3]
[CT=5]
[N=3]
[B=1]
[R=1]
[CB=4]
[CT=0]
[N=0]
[B=1]
[R=1]
[CB=4]
[CT=0]
[N=1]
[B=1]
[R=1]
[CB=4]
[CT=0]
[N=2]
[B=1]
[R=1]
[CB=4]
[CT=0]
[N=3]
[B=1]
[R=1]
[CB=4]
[CT=1]
[N=0]
[B=1]
[R=1]
[CB=4]
[CT=1]
[N=1]
[B=1]
[R=1]
[CB=4]
[CT=1]
[N=2]
[B=1]
[R=1]
[CB=4]
[CT=1]
[N=3]
[B=1]
[R=1]
[CB=4]
[CT=2]
[N=0]
[B=1]
[R=1]
[CB=4]
[CT=2]
[N=1]
[B=1]
[R=1]
[CB=4]
[CT=2]
[N=2]
[B=1]
[R=1]
[CB=4]
[CT=2]
[N=3]
[B=1]
[R=1]
[CB=4]
[CT=3]
[N=0]
[B=1]
[R=1]
[CB=4]
[CT=3]
[N=1]
R65
ct_coef
[T=1]
[B=1]
[R=1]
[CB=4]
[CT=3]
[N=2]
[T=1]
[B=1]
[R=1]
[CB=4]
[CT=3]
[N=3]
[T=1]
[B=1]
[R=1]
[CB=4]
[CT=4]
[N=0]
[T=1]
[B=1]
[R=1]
[CB=4]
[CT=4]
[N=1]
[T=1]
[B=1]
[R=1]
[CB=4]
[CT=4]
[N=2]
[T=1]
[B=1]
[R=1]
[CB=4]
[CT=4]
[N=3]
[T=1]
[B=1]
[R=1]
[CB=4]
[CT=5]
[N=0]
[T=1]
[B=1]
[R=1]
[CB=4]
[CT=5]
[N=1]
[T=1]
[B=1]
[R=1]
[CB=4]
[CT=5]
[N=2]
[T=1]
[B=1]
[R=1]
[CB=4]
[CT=5]
[N=3]
[T=1]
[B=1]
[R=1]
[CB=5]
[CT=0]
[N=0]
[T=1]
[B=1]
[R=1]
[CB=5]
[CT=0]
[N=1]
[T=1]
[B=1]
[R=1]
[CB=5]
[CT=0]
[N=2]
[T=1]
[B=1]
[R=1]
[CB=5]
[CT=0]
[N=3]
[T=1]
[B=1]
[R=1]
[CB=5]
[CT=1]
[N=0]
[T=1]
[B=1]
[R=1]
[CB=5]
[CT=1]
[N=1]
R66
ct_coef
[T=1]
[B=1]
[R=1]
[CB=5]
[CT=1]
[N=2]
[T=1]
[B=1]
[R=1]
[CB=5]
[CT=1]
[N=3]
[T=1]
[B=1]
[R=1]
[CB=5]
[CT=2]
[N=0]
[T=1]
[B=1]
[R=1]
[CB=5]
[CT=2]
[N=1]
[T=1]
[B=1]
[R=1]
[CB=5]
[CT=2]
[N=2]
[T=1]
[B=1]
[R=1]
[CB=5]
[CT=2]
[N=3]
[T=1]
[B=1]
[R=1]
[CB=5]
[CT=3]
[N=0]
[T=1]
[B=1]
[R=1]
[CB=5]
[CT=3]
[N=1]
[T=1]
[B=1]
[R=1]
[CB=5]
[CT=3]
[N=2]
[T=1]
[B=1]
[R=1]
[CB=5]
[CT=3]
[N=3]
[T=1]
[B=1]
[R=1]
[CB=5]
[CT=4]
[N=0]
[T=1]
[B=1]
[R=1]
[CB=5]
[CT=4]
[N=1]
[T=1]
[B=1]
[R=1]
[CB=5]
[CT=4]
[N=2]
[T=1]
[B=1]
[R=1]
[CB=5]
[CT=4]
[N=3]
[T=1]
[B=1]
[R=1]
[CB=5]
[CT=5]
[N=0]
[T=1]
[B=1]
[R=1]
[CB=5]
[CT=5]
[N=1]
R67
ct_coef
[T=1]
[B=1]
[R=1]
[T=1]
[B=1]
[R=1]
[T=2]
[B=0]
[R=0]
[T=2]
[B=0]
[R=0]
[T=2]
[B=0]
[R=0]
[T=2]
[B=0]
[R=0]
[T=2]
[B=0]
[R=0]
[T=2]
[B=0]
[R=0]
[T=2]
[B=0]
[R=0]
[T=2]
[B=0]
[R=0]
[T=2]
[B=0]
[R=0]
[T=2]
[B=0]
[R=0]
[T=2]
[B=0]
[R=0]
[T=2]
[B=0]
[R=0]
[T=2]
[B=0]
[R=0]
[T=2]
[B=0]
[R=0]
HEVC
22
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[CB=5]
[CT=5]
[N=2]
[CB=5]
[CT=5]
[N=3]
[CB=0]
[CT=0]
[N=0]
[CB=0]
[CT=0]
[N=1]
[CB=0]
[CT=0]
[N=2]
[CB=0]
[CT=0]
[N=3]
[CB=0]
[CT=1]
[N=0]
[CB=0]
[CT=1]
[N=1]
[CB=0]
[CT=1]
[N=2]
[CB=0]
[CT=1]
[N=3]
[CB=0]
[CT=2]
[N=0]
[CB=0]
[CT=2]
[N=1]
[CB=0]
[CT=2]
[N=2]
[CB=0]
[CT=2]
[N=3]
[CB=1]
[CT=0]
[N=0]
[CB=1]
[CT=0]
[N=1]
R68
ct_coef
[T=2]
[B=0]
[R=0]
[CB=1]
[CT=0]
[N=2]
[T=2]
[B=0]
[R=0]
[CB=1]
[CT=0]
[N=3]
[T=2]
[B=0]
[R=0]
[CB=1]
[CT=1]
[N=0]
[T=2]
[B=0]
[R=0]
[CB=1]
[CT=1]
[N=1]
[T=2]
[B=0]
[R=0]
[CB=1]
[CT=1]
[N=2]
[T=2]
[B=0]
[R=0]
[CB=1]
[CT=1]
[N=3]
[T=2]
[B=0]
[R=0]
[CB=1]
[CT=2]
[N=0]
[T=2]
[B=0]
[R=0]
[CB=1]
[CT=2]
[N=1]
[T=2]
[B=0]
[R=0]
[CB=1]
[CT=2]
[N=2]
[T=2]
[B=0]
[R=0]
[CB=1]
[CT=2]
[N=3]
[T=2]
[B=0]
[R=0]
[CB=1]
[CT=3]
[N=0]
[T=2]
[B=0]
[R=0]
[CB=1]
[CT=3]
[N=1]
[T=2]
[B=0]
[R=0]
[CB=1]
[CT=3]
[N=2]
[T=2]
[B=0]
[R=0]
[CB=1]
[CT=3]
[N=3]
[T=2]
[B=0]
[R=0]
[CB=1]
[CT=4]
[N=0]
[T=2]
[B=0]
[R=0]
[CB=1]
[CT=4]
[N=1]
R69
ct_coef
[T=2]
[B=0]
[R=0]
[CB=1]
[CT=4]
[N=2]
[T=2]
[B=0]
[R=0]
[CB=1]
[CT=4]
[N=3]
[T=2]
[B=0]
[R=0]
[CB=1]
[CT=5]
[N=0]
[T=2]
[B=0]
[R=0]
[CB=1]
[CT=5]
[N=1]
[T=2]
[B=0]
[R=0]
[CB=1]
[CT=5]
[N=2]
[T=2]
[B=0]
[R=0]
[CB=1]
[CT=5]
[N=3]
[T=2]
[B=0]
[R=0]
[CB=2]
[CT=0]
[N=0]
[T=2]
[B=0]
[R=0]
[CB=2]
[CT=0]
[N=1]
[T=2]
[B=0]
[R=0]
[CB=2]
[CT=0]
[N=2]
[T=2]
[B=0]
[R=0]
[CB=2]
[CT=0]
[N=3]
[T=2]
[B=0]
[R=0]
[CB=2]
[CT=1]
[N=0]
[T=2]
[B=0]
[R=0]
[CB=2]
[CT=1]
[N=1]
[T=2]
[B=0]
[R=0]
[CB=2]
[CT=1]
[N=2]
[T=2]
[B=0]
[R=0]
[CB=2]
[CT=1]
[N=3]
[T=2]
[B=0]
[R=0]
[CB=2]
[CT=2]
[N=0]
[T=2]
[B=0]
[R=0]
[CB=2]
[CT=2]
[N=1]
R70
ct_coef
[T=2]
[B=0]
[R=0]
[CB=2]
[CT=2]
[T=2]
[B=0]
[R=0]
[CB=2]
[T=2]
[B=0]
[R=0]
[CB=2]
[T=2]
[B=0]
[R=0]
[CB=2]
[T=2]
[B=0]
[R=0]
[CB=2]
[T=2]
[B=0]
[R=0]
[CB=2]
[T=2]
[B=0]
[R=0]
[CB=2]
[T=2]
[B=0]
[R=0]
[CB=2]
[T=2]
[B=0]
[R=0]
[CB=2]
[T=2]
[B=0]
[R=0]
[CB=2]
[T=2]
[B=0]
[R=0]
[CB=2]
[T=2]
[B=0]
[R=0]
[CB=2]
[T=2]
[B=0]
[R=0]
[CB=2]
[T=2]
[B=0]
[R=0]
[CB=2]
[T=2]
[B=0]
[R=0]
[CB=3]
[T=2]
[B=0]
[R=0]
[CB=3]
[CT=0]
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
23
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[N=2]
[CT=2]
[N=3]
[CT=3]
[N=0]
[CT=3]
[N=1]
[CT=3]
[N=2]
[CT=3]
[N=3]
[CT=4]
[N=0]
[CT=4]
[N=1]
[CT=4]
[N=2]
[CT=4]
[N=3]
[CT=5]
[N=0]
[CT=5]
[N=1]
[CT=5]
[N=2]
[CT=5]
[N=3]
[CT=0]
[N=0]
[N=1]
R71
ct_coef
[T=2]
[B=0]
[R=0]
[CB=3]
[CT=0]
[N=2]
[T=2]
[B=0]
[R=0]
[CB=3]
[CT=0]
[N=3]
[T=2]
[B=0]
[R=0]
[CB=3]
[CT=1]
[N=0]
[T=2]
[B=0]
[R=0]
[CB=3]
[CT=1]
[N=1]
[T=2]
[B=0]
[R=0]
[CB=3]
[CT=1]
[N=2]
[T=2]
[B=0]
[R=0]
[CB=3]
[CT=1]
[N=3]
[T=2]
[B=0]
[R=0]
[CB=3]
[CT=2]
[N=0]
[T=2]
[B=0]
[R=0]
[CB=3]
[CT=2]
[N=1]
[T=2]
[B=0]
[R=0]
[CB=3]
[CT=2]
[N=2]
[T=2]
[B=0]
[R=0]
[CB=3]
[CT=2]
[N=3]
[T=2]
[B=0]
[R=0]
[CB=3]
[CT=3]
[N=0]
[T=2]
[B=0]
[R=0]
[CB=3]
[CT=3]
[N=1]
[T=2]
[B=0]
[R=0]
[CB=3]
[CT=3]
[N=2]
[T=2]
[B=0]
[R=0]
[CB=3]
[CT=3]
[N=3]
[T=2]
[B=0]
[R=0]
[CB=3]
[CT=4]
[N=0]
[T=2]
[B=0]
[R=0]
[CB=3]
[CT=4]
[N=1]
R72
ct_coef
[T=2]
[B=0]
[R=0]
[CB=3]
[CT=4]
[N=2]
[T=2]
[B=0]
[R=0]
[CB=3]
[CT=4]
[N=3]
[T=2]
[B=0]
[R=0]
[CB=3]
[CT=5]
[N=0]
[T=2]
[B=0]
[R=0]
[CB=3]
[CT=5]
[N=1]
[T=2]
[B=0]
[R=0]
[CB=3]
[CT=5]
[N=2]
[T=2]
[B=0]
[R=0]
[CB=3]
[CT=5]
[N=3]
[T=2]
[B=0]
[R=0]
[CB=4]
[CT=0]
[N=0]
[T=2]
[B=0]
[R=0]
[CB=4]
[CT=0]
[N=1]
[T=2]
[B=0]
[R=0]
[CB=4]
[CT=0]
[N=2]
[T=2]
[B=0]
[R=0]
[CB=4]
[CT=0]
[N=3]
[T=2]
[B=0]
[R=0]
[CB=4]
[CT=1]
[N=0]
[T=2]
[B=0]
[R=0]
[CB=4]
[CT=1]
[N=1]
[T=2]
[B=0]
[R=0]
[CB=4]
[CT=1]
[N=2]
[T=2]
[B=0]
[R=0]
[CB=4]
[CT=1]
[N=3]
[T=2]
[B=0]
[R=0]
[CB=4]
[CT=2]
[N=0]
[T=2]
[B=0]
[R=0]
[CB=4]
[CT=2]
[N=1]
R73
ct_coef
[T=2]
[B=0]
[R=0]
[CB=4]
[CT=2]
[N=2]
[T=2]
[B=0]
[R=0]
[CB=4]
[CT=2]
[T=2]
[B=0]
[R=0]
[CB=4]
[CT=3]
[T=2]
[B=0]
[R=0]
[CB=4]
[CT=3]
[T=2]
[B=0]
[R=0]
[CB=4]
[CT=3]
[T=2]
[B=0]
[R=0]
[CB=4]
[CT=3]
[T=2]
[B=0]
[R=0]
[CB=4]
[CT=4]
[T=2]
[B=0]
[R=0]
[CB=4]
[CT=4]
[T=2]
[B=0]
[R=0]
[CB=4]
[CT=4]
[T=2]
[B=0]
[R=0]
[CB=4]
[CT=4]
[T=2]
[B=0]
[R=0]
[CB=4]
[CT=5]
[N=0]
[T=2]
[B=0]
[R=0]
[CB=4]
[CT=5]
[N=1]
[T=2]
[B=0]
[R=0]
[CB=4]
[CT=5]
[T=2]
[B=0]
[R=0]
[CB=4]
[CT=5]
[T=2]
[B=0]
[R=0]
[CB=5]
[CT=0]
[T=2]
[B=0]
[R=0]
[CB=5]
[CT=0]
[N=1]
HEVC
24
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[N=3]
[N=0]
[N=1]
[N=2]
[N=3]
[N=0]
[N=1]
[N=2]
[N=3]
[N=2]
[N=3]
[N=0]
R74
ct_coef
[T=2]
[B=0]
[R=0]
[CB=5]
[CT=0]
[N=2]
[T=2]
[B=0]
[R=0]
[CB=5]
[CT=0]
[N=3]
[T=2]
[B=0]
[R=0]
[CB=5]
[CT=1]
[N=0]
[T=2]
[B=0]
[R=0]
[CB=5]
[CT=1]
[N=1]
[T=2]
[B=0]
[R=0]
[CB=5]
[CT=1]
[N=2]
[T=2]
[B=0]
[R=0]
[CB=5]
[CT=1]
[N=3]
[T=2]
[B=0]
[R=0]
[CB=5]
[CT=2]
[N=0]
[T=2]
[B=0]
[R=0]
[CB=5]
[CT=2]
[N=1]
[T=2]
[B=0]
[R=0]
[CB=5]
[CT=2]
[N=2]
[T=2]
[B=0]
[R=0]
[CB=5]
[CT=2]
[N=3]
[T=2]
[B=0]
[R=0]
[CB=5]
[CT=3]
[N=0]
[T=2]
[B=0]
[R=0]
[CB=5]
[CT=3]
[N=1]
[T=2]
[B=0]
[R=0]
[CB=5]
[CT=3]
[N=2]
[T=2]
[B=0]
[R=0]
[CB=5]
[CT=3]
[N=3]
[T=2]
[B=0]
[R=0]
[CB=5]
[CT=4]
[N=0]
[T=2]
[B=0]
[R=0]
[CB=5]
[CT=4]
[N=1]
R75
ct_coef
[T=2]
[B=0]
[R=0]
[CB=5]
[CT=4]
[N=2]
[T=2]
[B=0]
[R=0]
[CB=5]
[CT=4]
[N=3]
[T=2]
[B=0]
[R=0]
[CB=5]
[CT=5]
[N=0]
[T=2]
[B=0]
[R=0]
[CB=5]
[CT=5]
[N=1]
[T=2]
[B=0]
[R=0]
[CB=5]
[CT=5]
[N=2]
[T=2]
[B=0]
[R=0]
[CB=5]
[CT=5]
[N=3]
[T=2]
[B=0]
[R=1]
[CB=0]
[CT=0]
[N=0]
[T=2]
[B=0]
[R=1]
[CB=0]
[CT=0]
[N=1]
[T=2]
[B=0]
[R=1]
[CB=0]
[CT=0]
[N=2]
[T=2]
[B=0]
[R=1]
[CB=0]
[CT=0]
[N=3]
[T=2]
[B=0]
[R=1]
[CB=0]
[CT=1]
[N=0]
[T=2]
[B=0]
[R=1]
[CB=0]
[CT=1]
[N=1]
[T=2]
[B=0]
[R=1]
[CB=0]
[CT=1]
[N=2]
[T=2]
[B=0]
[R=1]
[CB=0]
[CT=1]
[N=3]
[T=2]
[B=0]
[R=1]
[CB=0]
[CT=2]
[N=0]
[T=2]
[B=0]
[R=1]
[CB=0]
[CT=2]
[N=1]
R76
ct_coef
[T=2]
[B=0]
[R=1]
[CB=0]
[CT=2]
[N=2]
[T=2]
[B=0]
[R=1]
[CB=0]
[CT=2]
[N=3]
[T=2]
[B=0]
[R=1]
[CB=1]
[CT=0]
[N=0]
[T=2]
[B=0]
[R=1]
[CB=1]
[CT=0]
[N=1]
[T=2]
[B=0]
[R=1]
[CB=1]
[CT=0]
[N=2]
[T=2]
[B=0]
[R=1]
[CB=1]
[CT=0]
[N=3]
[T=2]
[B=0]
[R=1]
[CB=1]
[CT=1]
[N=0]
[T=2]
[B=0]
[R=1]
[CB=1]
[CT=1]
[N=1]
[T=2]
[B=0]
[R=1]
[CB=1]
[CT=1]
[N=2]
[T=2]
[B=0]
[R=1]
[CB=1]
[CT=1]
[N=3]
[T=2]
[B=0]
[R=1]
[CB=1]
[CT=2]
[N=0]
[T=2]
[B=0]
[R=1]
[CB=1]
[CT=2]
[N=1]
[T=2]
[B=0]
[R=1]
[CB=1]
[CT=2]
[N=2]
[T=2]
[B=0]
[R=1]
[CB=1]
[CT=2]
[N=3]
[T=2]
[B=0]
[R=1]
[CB=1]
[CT=3]
[N=0]
[T=2]
[B=0]
[R=1]
[CB=1]
[CT=3]
[N=1]
R77
ct_coef
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
25
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[T=2]
[B=0]
[R=1]
[CB=1]
[CT=3]
[N=2]
[T=2]
[B=0]
[R=1]
[CB=1]
[CT=3]
[N=3]
[T=2]
[B=0]
[R=1]
[CB=1]
[CT=4]
[N=0]
[T=2]
[B=0]
[R=1]
[CB=1]
[CT=4]
[N=1]
[T=2]
[B=0]
[R=1]
[CB=1]
[CT=4]
[N=2]
[T=2]
[B=0]
[R=1]
[CB=1]
[CT=4]
[N=3]
[T=2]
[B=0]
[R=1]
[CB=1]
[CT=5]
[N=0]
[T=2]
[B=0]
[R=1]
[CB=1]
[CT=5]
[N=1]
[T=2]
[B=0]
[R=1]
[CB=1]
[CT=5]
[N=2]
[T=2]
[B=0]
[R=1]
[CB=1]
[CT=5]
[N=3]
[T=2]
[B=0]
[R=1]
[CB=2]
[CT=0]
[N=0]
[T=2]
[B=0]
[R=1]
[CB=2]
[CT=0]
[N=1]
[T=2]
[B=0]
[R=1]
[CB=2]
[CT=0]
[N=2]
[T=2]
[B=0]
[R=1]
[CB=2]
[CT=0]
[N=3]
[T=2]
[B=0]
[R=1]
[CB=2]
[CT=1]
[N=0]
[T=2]
[B=0]
[R=1]
[CB=2]
[CT=1]
[N=1]
R78
ct_coef
[T=2]
[B=0]
[R=1]
[CB=2]
[CT=1]
[N=2]
[T=2]
[B=0]
[R=1]
[CB=2]
[CT=1]
[N=3]
[T=2]
[B=0]
[R=1]
[CB=2]
[CT=2]
[N=0]
[T=2]
[B=0]
[R=1]
[CB=2]
[CT=2]
[N=1]
[T=2]
[B=0]
[R=1]
[CB=2]
[CT=2]
[N=2]
[T=2]
[B=0]
[R=1]
[CB=2]
[CT=2]
[N=3]
[T=2]
[B=0]
[R=1]
[CB=2]
[CT=3]
[N=0]
[T=2]
[B=0]
[R=1]
[CB=2]
[CT=3]
[N=1]
[T=2]
[B=0]
[R=1]
[CB=2]
[CT=3]
[N=2]
[T=2]
[B=0]
[R=1]
[CB=2]
[CT=3]
[N=3]
[T=2]
[B=0]
[R=1]
[CB=2]
[CT=4]
[N=0]
[T=2]
[B=0]
[R=1]
[CB=2]
[CT=4]
[N=1]
[T=2]
[B=0]
[R=1]
[CB=2]
[CT=4]
[N=2]
[T=2]
[B=0]
[R=1]
[CB=2]
[CT=4]
[N=3]
[T=2]
[B=0]
[R=1]
[CB=2]
[CT=5]
[N=0]
[T=2]
[B=0]
[R=1]
[CB=2]
[CT=5]
[N=1]
R79
ct_coef
[T=2]
[B=0]
[R=1]
[CB=2]
[CT=5]
[N=2]
[T=2]
[B=0]
[R=1]
[CB=2]
[CT=5]
[N=3]
[T=2]
[B=0]
[R=1]
[CB=3]
[CT=0]
[N=0]
[T=2]
[B=0]
[R=1]
[CB=3]
[CT=0]
[N=1]
[T=2]
[B=0]
[R=1]
[CB=3]
[CT=0]
[N=2]
[T=2]
[B=0]
[R=1]
[CB=3]
[CT=0]
[N=3]
[T=2]
[B=0]
[R=1]
[CB=3]
[CT=1]
[N=0]
[T=2]
[B=0]
[R=1]
[CB=3]
[CT=1]
[N=1]
[T=2]
[B=0]
[R=1]
[CB=3]
[CT=1]
[N=2]
[T=2]
[B=0]
[R=1]
[CB=3]
[CT=1]
[N=3]
[T=2]
[B=0]
[R=1]
[CB=3]
[CT=2]
[N=0]
[T=2]
[B=0]
[R=1]
[CB=3]
[CT=2]
[N=1]
[T=2]
[B=0]
[R=1]
[CB=3]
[CT=2]
[N=2]
[T=2]
[B=0]
[R=1]
[CB=3]
[CT=2]
[N=3]
[T=2]
[B=0]
[R=1]
[CB=3]
[CT=3]
[N=0]
[T=2]
[B=0]
[R=1]
[CB=3]
[CT=3]
[N=1]
R80
ct_coef
[T=2]
[B=0]
[T=2]
[B=0]
[T=2]
[B=0]
[T=2]
[B=0]
[T=2]
[B=0]
[T=2]
[B=0]
[T=2]
[B=0]
[T=2]
[B=0]
[T=2]
[B=0]
[T=2]
[B=0]
[T=2]
[B=0]
[T=2]
[B=0]
[T=2]
[B=0]
[T=2]
[B=0]
[T=2]
[B=0]
[T=2]
[B=0]
HEVC
26
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[R=1]
[CB=3]
[CT=3]
[N=2]
[R=1]
[CB=3]
[CT=3]
[N=3]
[R=1]
[CB=3]
[CT=4]
[N=0]
[R=1]
[CB=3]
[CT=4]
[N=1]
[R=1]
[CB=3]
[CT=4]
[N=2]
[R=1]
[CB=3]
[CT=4]
[N=3]
[R=1]
[CB=3]
[CT=5]
[N=0]
[R=1]
[CB=3]
[CT=5]
[N=1]
[R=1]
[CB=3]
[CT=5]
[N=2]
[R=1]
[CB=3]
[CT=5]
[N=3]
[R=1]
[CB=4]
[CT=0]
[N=0]
[R=1]
[CB=4]
[CT=0]
[N=1]
[R=1]
[CB=4]
[CT=0]
[N=2]
[R=1]
[CB=4]
[CT=0]
[N=3]
[R=1]
[CB=4]
[CT=1]
[N=0]
[R=1]
[CB=4]
[CT=1]
[N=1]
R81
ct_coef
[T=2]
[B=0]
[R=1]
[CB=4]
[CT=1]
[N=2]
[T=2]
[B=0]
[R=1]
[CB=4]
[CT=1]
[N=3]
[T=2]
[B=0]
[R=1]
[CB=4]
[CT=2]
[N=0]
[T=2]
[B=0]
[R=1]
[CB=4]
[CT=2]
[N=1]
[T=2]
[B=0]
[R=1]
[CB=4]
[CT=2]
[N=2]
[T=2]
[B=0]
[R=1]
[CB=4]
[CT=2]
[N=3]
[T=2]
[B=0]
[R=1]
[CB=4]
[CT=3]
[N=0]
[T=2]
[B=0]
[R=1]
[CB=4]
[CT=3]
[N=1]
[T=2]
[B=0]
[R=1]
[CB=4]
[CT=3]
[N=2]
[T=2]
[B=0]
[R=1]
[CB=4]
[CT=3]
[N=3]
[T=2]
[B=0]
[R=1]
[CB=4]
[CT=4]
[N=0]
[T=2]
[B=0]
[R=1]
[CB=4]
[CT=4]
[N=1]
[T=2]
[B=0]
[R=1]
[CB=4]
[CT=4]
[N=2]
[T=2]
[B=0]
[R=1]
[CB=4]
[CT=4]
[N=3]
[T=2]
[B=0]
[R=1]
[CB=4]
[CT=5]
[N=0]
[T=2]
[B=0]
[R=1]
[CB=4]
[CT=5]
[N=1]
R82
ct_coef
[T=2]
[B=0]
[R=1]
[CB=4]
[CT=5]
[N=2]
[T=2]
[B=0]
[R=1]
[CB=4]
[CT=5]
[N=3]
[T=2]
[B=0]
[R=1]
[CB=5]
[CT=0]
[N=0]
[T=2]
[B=0]
[R=1]
[CB=5]
[CT=0]
[N=1]
[T=2]
[B=0]
[R=1]
[CB=5]
[CT=0]
[N=2]
[T=2]
[B=0]
[R=1]
[CB=5]
[CT=0]
[N=3]
[T=2]
[B=0]
[R=1]
[CB=5]
[CT=1]
[N=0]
[T=2]
[B=0]
[R=1]
[CB=5]
[CT=1]
[N=1]
[T=2]
[B=0]
[R=1]
[CB=5]
[CT=1]
[N=2]
[T=2]
[B=0]
[R=1]
[CB=5]
[CT=1]
[N=3]
[T=2]
[B=0]
[R=1]
[CB=5]
[CT=2]
[N=0]
[T=2]
[B=0]
[R=1]
[CB=5]
[CT=2]
[N=1]
[T=2]
[B=0]
[R=1]
[CB=5]
[CT=2]
[N=2]
[T=2]
[B=0]
[R=1]
[CB=5]
[CT=2]
[N=3]
[T=2]
[B=0]
[R=1]
[CB=5]
[CT=3]
[N=0]
[T=2]
[B=0]
[R=1]
[CB=5]
[CT=3]
[N=1]
R83
ct_coef
[T=2]
[B=0]
[R=1]
[CB=5]
[T=2]
[B=0]
[R=1]
[T=2]
[B=0]
[R=1]
[T=2]
[B=0]
[R=1]
[T=2]
[B=0]
[R=1]
[T=2]
[B=0]
[R=1]
[T=2]
[B=0]
[R=1]
[T=2]
[B=0]
[R=1]
[T=2]
[B=0]
[R=1]
[T=2]
[B=0]
[R=1]
[T=2]
[B=1]
[R=0]
[T=2]
[B=1]
[R=0]
[T=2]
[B=1]
[R=0]
[T=2]
[B=1]
[R=0]
[T=2]
[B=1]
[R=0]
[T=2]
[B=1]
[R=0]
[CB=0]
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
27
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[CT=3]
[N=2]
[CB=5]
[CT=3]
[N=3]
[CB=5]
[CT=4]
[N=0]
[CB=5]
[CT=4]
[N=1]
[CB=5]
[CT=4]
[N=2]
[CB=5]
[CT=4]
[N=3]
[CB=5]
[CT=5]
[N=0]
[CB=5]
[CT=5]
[N=1]
[CB=5]
[CT=5]
[N=2]
[CB=5]
[CT=5]
[N=3]
[CB=0]
[CT=0]
[N=0]
[CB=0]
[CT=0]
[N=1]
[CB=0]
[CT=0]
[N=2]
[CB=0]
[CT=0]
[N=3]
[CB=0]
[CT=1]
[N=0]
[CT=1]
[N=1]
R84
ct_coef
[T=2]
[B=1]
[R=0]
[CB=0]
[CT=1]
[N=2]
[T=2]
[B=1]
[R=0]
[CB=0]
[CT=1]
[N=3]
[T=2]
[B=1]
[R=0]
[CB=0]
[CT=2]
[N=0]
[T=2]
[B=1]
[R=0]
[CB=0]
[CT=2]
[N=1]
[T=2]
[B=1]
[R=0]
[CB=0]
[CT=2]
[N=2]
[T=2]
[B=1]
[R=0]
[CB=0]
[CT=2]
[N=3]
[T=2]
[B=1]
[R=0]
[CB=1]
[CT=0]
[N=0]
[T=2]
[B=1]
[R=0]
[CB=1]
[CT=0]
[N=1]
[T=2]
[B=1]
[R=0]
[CB=1]
[CT=0]
[N=2]
[T=2]
[B=1]
[R=0]
[CB=1]
[CT=0]
[N=3]
[T=2]
[B=1]
[R=0]
[CB=1]
[CT=1]
[N=0]
[T=2]
[B=1]
[R=0]
[CB=1]
[CT=1]
[N=1]
[T=2]
[B=1]
[R=0]
[CB=1]
[CT=1]
[N=2]
[T=2]
[B=1]
[R=0]
[CB=1]
[CT=1]
[N=3]
[T=2]
[B=1]
[R=0]
[CB=1]
[CT=2]
[N=0]
[T=2]
[B=1]
[R=0]
[CB=1]
[CT=2]
[N=1]
R85
ct_coef
[T=2]
[B=1]
[R=0]
[CB=1]
[CT=2]
[N=2]
[T=2]
[B=1]
[R=0]
[CB=1]
[CT=2]
[N=3]
[T=2]
[B=1]
[R=0]
[CB=1]
[CT=3]
[N=0]
[T=2]
[B=1]
[R=0]
[CB=1]
[CT=3]
[N=1]
[T=2]
[B=1]
[R=0]
[CB=1]
[CT=3]
[N=2]
[T=2]
[B=1]
[R=0]
[CB=1]
[CT=3]
[N=3]
[T=2]
[B=1]
[R=0]
[CB=1]
[CT=4]
[N=0]
[T=2]
[B=1]
[R=0]
[CB=1]
[CT=4]
[N=1]
[T=2]
[B=1]
[R=0]
[CB=1]
[CT=4]
[N=2]
[T=2]
[B=1]
[R=0]
[CB=1]
[CT=4]
[N=3]
[T=2]
[B=1]
[R=0]
[CB=1]
[CT=5]
[N=0]
[T=2]
[B=1]
[R=0]
[CB=1]
[CT=5]
[N=1]
[T=2]
[B=1]
[R=0]
[CB=1]
[CT=5]
[N=2]
[T=2]
[B=1]
[R=0]
[CB=1]
[CT=5]
[N=3]
[T=2]
[B=1]
[R=0]
[CB=2]
[CT=0]
[N=0]
[T=2]
[B=1]
[R=0]
[CB=2]
[CT=0]
[N=1]
R86
ct_coef
[T=2]
[B=1]
[R=0]
[CB=2]
[CT=0]
[N=2]
[T=2]
[B=1]
[R=0]
[CB=2]
[T=2]
[B=1]
[R=0]
[CB=2]
[T=2]
[B=1]
[R=0]
[CB=2]
[T=2]
[B=1]
[R=0]
[CB=2]
[T=2]
[B=1]
[R=0]
[CB=2]
[T=2]
[B=1]
[R=0]
[CB=2]
[T=2]
[B=1]
[R=0]
[CB=2]
[T=2]
[B=1]
[R=0]
[CB=2]
[T=2]
[B=1]
[R=0]
[CB=2]
[T=2]
[B=1]
[R=0]
[CB=2]
[CT=3]
[T=2]
[B=1]
[R=0]
[CB=2]
[CT=3]
[T=2]
[B=1]
[R=0]
[CB=2]
[T=2]
[B=1]
[R=0]
[CB=2]
[T=2]
[B=1]
[R=0]
[CB=2]
[T=2]
[B=1]
[R=0]
[CB=2]
[CT=4]
[N=1]
HEVC
28
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[CT=0]
[N=3]
[CT=1]
[N=0]
[CT=1]
[N=1]
[CT=1]
[N=2]
[CT=1]
[N=3]
[CT=2]
[N=0]
[CT=2]
[N=1]
[CT=2]
[N=2]
[CT=2]
[N=3]
[N=0]
[N=1]
[CT=3]
[N=2]
[CT=3]
[N=3]
[CT=4]
[N=0]
R87
ct_coef
[T=2]
[B=1]
[R=0]
[CB=2]
[CT=4]
[N=2]
[T=2]
[B=1]
[R=0]
[CB=2]
[CT=4]
[N=3]
[T=2]
[B=1]
[R=0]
[CB=2]
[CT=5]
[N=0]
[T=2]
[B=1]
[R=0]
[CB=2]
[CT=5]
[N=1]
[T=2]
[B=1]
[R=0]
[CB=2]
[CT=5]
[N=2]
[T=2]
[B=1]
[R=0]
[CB=2]
[CT=5]
[N=3]
[T=2]
[B=1]
[R=0]
[CB=3]
[CT=0]
[N=0]
[T=2]
[B=1]
[R=0]
[CB=3]
[CT=0]
[N=1]
[T=2]
[B=1]
[R=0]
[CB=3]
[CT=0]
[N=2]
[T=2]
[B=1]
[R=0]
[CB=3]
[CT=0]
[N=3]
[T=2]
[B=1]
[R=0]
[CB=3]
[CT=1]
[N=0]
[T=2]
[B=1]
[R=0]
[CB=3]
[CT=1]
[N=1]
[T=2]
[B=1]
[R=0]
[CB=3]
[CT=1]
[N=2]
[T=2]
[B=1]
[R=0]
[CB=3]
[CT=1]
[N=3]
[T=2]
[B=1]
[R=0]
[CB=3]
[CT=2]
[N=0]
[T=2]
[B=1]
[R=0]
[CB=3]
[CT=2]
[N=1]
R88
ct_coef
[T=2]
[B=1]
[R=0]
[CB=3]
[CT=2]
[N=2]
[T=2]
[B=1]
[R=0]
[CB=3]
[CT=2]
[N=3]
[T=2]
[B=1]
[R=0]
[CB=3]
[CT=3]
[N=0]
[T=2]
[B=1]
[R=0]
[CB=3]
[CT=3]
[N=1]
[T=2]
[B=1]
[R=0]
[CB=3]
[CT=3]
[N=2]
[T=2]
[B=1]
[R=0]
[CB=3]
[CT=3]
[N=3]
[T=2]
[B=1]
[R=0]
[CB=3]
[CT=4]
[N=0]
[T=2]
[B=1]
[R=0]
[CB=3]
[CT=4]
[N=1]
[T=2]
[B=1]
[R=0]
[CB=3]
[CT=4]
[N=2]
[T=2]
[B=1]
[R=0]
[CB=3]
[CT=4]
[N=3]
[T=2]
[B=1]
[R=0]
[CB=3]
[CT=5]
[N=0]
[T=2]
[B=1]
[R=0]
[CB=3]
[CT=5]
[N=1]
[T=2]
[B=1]
[R=0]
[CB=3]
[CT=5]
[N=2]
[T=2]
[B=1]
[R=0]
[CB=3]
[CT=5]
[N=3]
[T=2]
[B=1]
[R=0]
[CB=4]
[CT=0]
[N=0]
[T=2]
[B=1]
[R=0]
[CB=4]
[CT=0]
[N=1]
R89
ct_coef
[T=2]
[B=1]
[R=0]
[CB=4]
[CT=0]
[N=2]
[T=2]
[B=1]
[R=0]
[CB=4]
[CT=0]
[N=3]
[T=2]
[B=1]
[R=0]
[CB=4]
[CT=1]
[N=0]
[T=2]
[B=1]
[R=0]
[CB=4]
[CT=1]
[N=1]
[T=2]
[B=1]
[R=0]
[CB=4]
[CT=1]
[N=2]
[T=2]
[B=1]
[R=0]
[CB=4]
[CT=1]
[N=3]
[T=2]
[B=1]
[R=0]
[CB=4]
[CT=2]
[N=0]
[T=2]
[B=1]
[R=0]
[CB=4]
[CT=2]
[N=1]
[T=2]
[B=1]
[R=0]
[CB=4]
[CT=2]
[N=2]
[T=2]
[B=1]
[R=0]
[CB=4]
[CT=2]
[N=3]
[T=2]
[B=1]
[R=0]
[CB=4]
[CT=3]
[N=0]
[T=2]
[B=1]
[R=0]
[CB=4]
[CT=3]
[N=1]
[T=2]
[B=1]
[R=0]
[CB=4]
[CT=3]
[N=2]
[T=2]
[B=1]
[R=0]
[CB=4]
[CT=3]
[N=3]
[T=2]
[B=1]
[R=0]
[CB=4]
[CT=4]
[N=0]
[T=2]
[B=1]
[R=0]
[CB=4]
[CT=4]
[N=1]
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
29
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R90
ct_coef
[T=2]
[B=1]
[R=0]
[CB=4]
[CT=4]
[N=2]
[T=2]
[B=1]
[R=0]
[CB=4]
[CT=4]
[N=3]
[T=2]
[B=1]
[R=0]
[CB=4]
[CT=5]
[N=0]
[T=2]
[B=1]
[R=0]
[CB=4]
[CT=5]
[N=1]
[T=2]
[B=1]
[R=0]
[CB=4]
[CT=5]
[N=2]
[T=2]
[B=1]
[R=0]
[CB=4]
[CT=5]
[N=3]
[T=2]
[B=1]
[R=0]
[CB=5]
[CT=0]
[N=0]
[T=2]
[B=1]
[R=0]
[CB=5]
[CT=0]
[N=1]
[T=2]
[B=1]
[R=0]
[CB=5]
[CT=0]
[N=2]
[T=2]
[B=1]
[R=0]
[CB=5]
[CT=0]
[N=3]
[T=2]
[B=1]
[R=0]
[CB=5]
[CT=1]
[N=0]
[T=2]
[B=1]
[R=0]
[CB=5]
[CT=1]
[N=1]
[T=2]
[B=1]
[R=0]
[CB=5]
[CT=1]
[N=2]
[T=2]
[B=1]
[R=0]
[CB=5]
[CT=1]
[N=3]
[T=2]
[B=1]
[R=0]
[CB=5]
[CT=2]
[N=0]
[T=2]
[B=1]
[R=0]
[CB=5]
[CT=2]
[N=1]
R91
ct_coef
[T=2]
[B=1]
[R=0]
[CB=5]
[CT=2]
[N=2]
[T=2]
[B=1]
[R=0]
[CB=5]
[CT=2]
[N=3]
[T=2]
[B=1]
[R=0]
[CB=5]
[CT=3]
[N=0]
[T=2]
[B=1]
[R=0]
[CB=5]
[CT=3]
[N=1]
[T=2]
[B=1]
[R=0]
[CB=5]
[CT=3]
[N=2]
[T=2]
[B=1]
[R=0]
[CB=5]
[CT=3]
[N=3]
[T=2]
[B=1]
[R=0]
[CB=5]
[CT=4]
[N=0]
[T=2]
[B=1]
[R=0]
[CB=5]
[CT=4]
[N=1]
[T=2]
[B=1]
[R=0]
[CB=5]
[CT=4]
[N=2]
[T=2]
[B=1]
[R=0]
[CB=5]
[CT=4]
[N=3]
[T=2]
[B=1]
[R=0]
[CB=5]
[CT=5]
[N=0]
[T=2]
[B=1]
[R=0]
[CB=5]
[CT=5]
[N=1]
[T=2]
[B=1]
[R=0]
[CB=5]
[CT=5]
[N=2]
[T=2]
[B=1]
[R=0]
[CB=5]
[CT=5]
[N=3]
[T=2]
[B=1]
[R=1]
[CB=0]
[CT=0]
[N=0]
[T=2]
[B=1]
[R=1]
[CB=0]
[CT=0]
[N=1]
R92
ct_coef
[T=2]
[B=1]
[R=1]
[CB=0]
[CT=0]
[N=2]
[T=2]
[B=1]
[R=1]
[CB=0]
[CT=0]
[N=3]
[T=2]
[B=1]
[R=1]
[CB=0]
[CT=1]
[N=0]
[T=2]
[B=1]
[R=1]
[CB=0]
[CT=1]
[N=1]
[T=2]
[B=1]
[R=1]
[CB=0]
[CT=1]
[N=2]
[T=2]
[B=1]
[R=1]
[CB=0]
[CT=1]
[N=3]
[T=2]
[B=1]
[R=1]
[CB=0]
[CT=2]
[N=0]
[T=2]
[B=1]
[R=1]
[CB=0]
[CT=2]
[N=1]
[T=2]
[B=1]
[R=1]
[CB=0]
[CT=2]
[N=2]
[T=2]
[B=1]
[R=1]
[CB=0]
[CT=2]
[N=3]
[T=2]
[B=1]
[R=1]
[CB=1]
[CT=0]
[N=0]
[T=2]
[B=1]
[R=1]
[CB=1]
[CT=0]
[N=1]
[T=2]
[B=1]
[R=1]
[CB=1]
[CT=0]
[N=2]
[T=2]
[B=1]
[R=1]
[CB=1]
[CT=0]
[N=3]
[T=2]
[B=1]
[R=1]
[CB=1]
[CT=1]
[N=0]
[T=2]
[B=1]
[R=1]
[CB=1]
[CT=1]
[N=1]
R93
ct_coef
[T=2]
[T=2]
[T=2]
[T=2]
[T=2]
[T=2]
[T=2]
[T=2]
[T=2]
[T=2]
[T=2]
[T=2]
[T=2]
[T=2]
[T=2]
[T=2]
HEVC
30
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[B=1]
[R=1]
[CB=1]
[CT=1]
[N=2]
[B=1]
[R=1]
[CB=1]
[CT=1]
[N=3]
[B=1]
[R=1]
[CB=1]
[CT=2]
[N=0]
[B=1]
[R=1]
[CB=1]
[CT=2]
[N=1]
[B=1]
[R=1]
[CB=1]
[CT=2]
[N=2]
[B=1]
[R=1]
[CB=1]
[CT=2]
[N=3]
[B=1]
[R=1]
[CB=1]
[CT=3]
[N=0]
[B=1]
[R=1]
[CB=1]
[CT=3]
[N=1]
[B=1]
[R=1]
[CB=1]
[CT=3]
[N=2]
[B=1]
[R=1]
[CB=1]
[CT=3]
[N=3]
[B=1]
[R=1]
[CB=1]
[CT=4]
[N=0]
[B=1]
[R=1]
[CB=1]
[CT=4]
[N=1]
[B=1]
[R=1]
[CB=1]
[CT=4]
[N=2]
[B=1]
[R=1]
[CB=1]
[CT=4]
[N=3]
[B=1]
[R=1]
[CB=1]
[CT=5]
[N=0]
[B=1]
[R=1]
[CB=1]
[CT=5]
[N=1]
R94
ct_coef
[T=2]
[B=1]
[R=1]
[CB=1]
[CT=5]
[N=2]
[T=2]
[B=1]
[R=1]
[CB=1]
[CT=5]
[N=3]
[T=2]
[B=1]
[R=1]
[CB=2]
[CT=0]
[N=0]
[T=2]
[B=1]
[R=1]
[CB=2]
[CT=0]
[N=1]
[T=2]
[B=1]
[R=1]
[CB=2]
[CT=0]
[N=2]
[T=2]
[B=1]
[R=1]
[CB=2]
[CT=0]
[N=3]
[T=2]
[B=1]
[R=1]
[CB=2]
[CT=1]
[N=0]
[T=2]
[B=1]
[R=1]
[CB=2]
[CT=1]
[N=1]
[T=2]
[B=1]
[R=1]
[CB=2]
[CT=1]
[N=2]
[T=2]
[B=1]
[R=1]
[CB=2]
[CT=1]
[N=3]
[T=2]
[B=1]
[R=1]
[CB=2]
[CT=2]
[N=0]
[T=2]
[B=1]
[R=1]
[CB=2]
[CT=2]
[N=1]
[T=2]
[B=1]
[R=1]
[CB=2]
[CT=2]
[N=2]
[T=2]
[B=1]
[R=1]
[CB=2]
[CT=2]
[N=3]
[T=2]
[B=1]
[R=1]
[CB=2]
[CT=3]
[N=0]
[T=2]
[B=1]
[R=1]
[CB=2]
[CT=3]
[N=1]
R95
ct_coef
[T=2]
[B=1]
[R=1]
[CB=2]
[CT=3]
[N=2]
[T=2]
[B=1]
[R=1]
[CB=2]
[CT=3]
[N=3]
[T=2]
[B=1]
[R=1]
[CB=2]
[CT=4]
[N=0]
[T=2]
[B=1]
[R=1]
[CB=2]
[CT=4]
[N=1]
[T=2]
[B=1]
[R=1]
[CB=2]
[CT=4]
[N=2]
[T=2]
[B=1]
[R=1]
[CB=2]
[CT=4]
[N=3]
[T=2]
[B=1]
[R=1]
[CB=2]
[CT=5]
[N=0]
[T=2]
[B=1]
[R=1]
[CB=2]
[CT=5]
[N=1]
[T=2]
[B=1]
[R=1]
[CB=2]
[CT=5]
[N=2]
[T=2]
[B=1]
[R=1]
[CB=2]
[CT=5]
[N=3]
[T=2]
[B=1]
[R=1]
[CB=3]
[CT=0]
[N=0]
[T=2]
[B=1]
[R=1]
[CB=3]
[CT=0]
[N=1]
[T=2]
[B=1]
[R=1]
[CB=3]
[CT=0]
[N=2]
[T=2]
[B=1]
[R=1]
[CB=3]
[CT=0]
[N=3]
[T=2]
[B=1]
[R=1]
[CB=3]
[CT=1]
[N=0]
[T=2]
[B=1]
[R=1]
[CB=3]
[CT=1]
[N=1]
R96
ct_coef
[T=2]
[B=1]
[R=1]
[T=2]
[B=1]
[R=1]
[T=2]
[B=1]
[R=1]
[T=2]
[B=1]
[R=1]
[T=2]
[B=1]
[R=1]
[T=2]
[B=1]
[R=1]
[T=2]
[B=1]
[R=1]
[T=2]
[B=1]
[R=1]
[T=2]
[B=1]
[R=1]
[T=2]
[B=1]
[R=1]
[T=2]
[B=1]
[R=1]
[T=2]
[B=1]
[R=1]
[T=2]
[B=1]
[R=1]
[T=2]
[B=1]
[R=1]
[T=2]
[B=1]
[R=1]
[T=2]
[B=1]
[R=1]
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
31
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[CB=3]
[CT=1]
[N=2]
[CB=3]
[CT=1]
[N=3]
[CB=3]
[CT=2]
[N=0]
[CB=3]
[CT=2]
[N=1]
[CB=3]
[CT=2]
[N=2]
[CB=3]
[CT=2]
[N=3]
[CB=3]
[CT=3]
[N=0]
[CB=3]
[CT=3]
[N=1]
[CB=3]
[CT=3]
[N=2]
[CB=3]
[CT=3]
[N=3]
[CB=3]
[CT=4]
[N=0]
[CB=3]
[CT=4]
[N=1]
[CB=3]
[CT=4]
[N=2]
[CB=3]
[CT=4]
[N=3]
[CB=3]
[CT=5]
[N=0]
[CB=3]
[CT=5]
[N=1]
R97
ct_coef
[T=2]
[B=1]
[R=1]
[CB=3]
[CT=5]
[N=2]
[T=2]
[B=1]
[R=1]
[CB=3]
[CT=5]
[N=3]
[T=2]
[B=1]
[R=1]
[CB=4]
[CT=0]
[N=0]
[T=2]
[B=1]
[R=1]
[CB=4]
[CT=0]
[N=1]
[T=2]
[B=1]
[R=1]
[CB=4]
[CT=0]
[N=2]
[T=2]
[B=1]
[R=1]
[CB=4]
[CT=0]
[N=3]
[T=2]
[B=1]
[R=1]
[CB=4]
[CT=1]
[N=0]
[T=2]
[B=1]
[R=1]
[CB=4]
[CT=1]
[N=1]
[T=2]
[B=1]
[R=1]
[CB=4]
[CT=1]
[N=2]
[T=2]
[B=1]
[R=1]
[CB=4]
[CT=1]
[N=3]
[T=2]
[B=1]
[R=1]
[CB=4]
[CT=2]
[N=0]
[T=2]
[B=1]
[R=1]
[CB=4]
[CT=2]
[N=1]
[T=2]
[B=1]
[R=1]
[CB=4]
[CT=2]
[N=2]
[T=2]
[B=1]
[R=1]
[CB=4]
[CT=2]
[N=3]
[T=2]
[B=1]
[R=1]
[CB=4]
[CT=3]
[N=0]
[T=2]
[B=1]
[R=1]
[CB=4]
[CT=3]
[N=1]
R98
ct_coef
[T=2]
[B=1]
[R=1]
[CB=4]
[CT=3]
[N=2]
[T=2]
[B=1]
[R=1]
[CB=4]
[CT=3]
[N=3]
[T=2]
[B=1]
[R=1]
[CB=4]
[CT=4]
[N=0]
[T=2]
[B=1]
[R=1]
[CB=4]
[CT=4]
[N=1]
[T=2]
[B=1]
[R=1]
[CB=4]
[CT=4]
[N=2]
[T=2]
[B=1]
[R=1]
[CB=4]
[CT=4]
[N=3]
[T=2]
[B=1]
[R=1]
[CB=4]
[CT=5]
[N=0]
[T=2]
[B=1]
[R=1]
[CB=4]
[CT=5]
[N=1]
[T=2]
[B=1]
[R=1]
[CB=4]
[CT=5]
[N=2]
[T=2]
[B=1]
[R=1]
[CB=4]
[CT=5]
[N=3]
[T=2]
[B=1]
[R=1]
[CB=5]
[CT=0]
[N=0]
[T=2]
[B=1]
[R=1]
[CB=5]
[CT=0]
[N=1]
[T=2]
[B=1]
[R=1]
[CB=5]
[CT=0]
[N=2]
[T=2]
[B=1]
[R=1]
[CB=5]
[CT=0]
[N=3]
[T=2]
[B=1]
[R=1]
[CB=5]
[CT=1]
[N=0]
[T=2]
[B=1]
[R=1]
[CB=5]
[CT=1]
[N=1]
R99
ct_coef
[T=2]
[B=1]
[R=1]
[CB=5]
[CT=1]
[T=2]
[B=1]
[R=1]
[CB=5]
[T=2]
[B=1]
[R=1]
[CB=5]
[T=2]
[B=1]
[R=1]
[CB=5]
[T=2]
[B=1]
[R=1]
[CB=5]
[T=2]
[B=1]
[R=1]
[CB=5]
[T=2]
[B=1]
[R=1]
[CB=5]
[T=2]
[B=1]
[R=1]
[CB=5]
[T=2]
[B=1]
[R=1]
[CB=5]
[T=2]
[B=1]
[R=1]
[CB=5]
[T=2]
[B=1]
[R=1]
[CB=5]
[T=2]
[B=1]
[R=1]
[CB=5]
[T=2]
[B=1]
[R=1]
[CB=5]
[T=2]
[B=1]
[R=1]
[CB=5]
[T=2]
[B=1]
[R=1]
[CB=5]
[T=2]
[B=1]
[R=1]
[CB=5]
[CT=5]
HEVC
32
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[N=2]
[CT=1]
[N=3]
[CT=2]
[N=0]
[CT=2]
[N=1]
[CT=2]
[N=2]
[CT=2]
[N=3]
[CT=3]
[N=0]
[CT=3]
[N=1]
[CT=3]
[N=2]
[CT=3]
[N=3]
[CT=4]
[N=0]
[CT=4]
[N=1]
[CT=4]
[N=2]
[CT=4]
[N=3]
[CT=5]
[N=0]
[N=1]
R100
ct_coef
[T=2]
[B=1]
[R=1]
[CB=5]
[CT=5]
[N=2]
[T=2]
[B=1]
[R=1]
[CB=5]
[CT=5]
[N=3]
[T=3]
[B=0]
[R=0]
[CB=0]
[CT=0]
[N=0]
[T=3]
[B=0]
[R=0]
[CB=0]
[CT=0]
[N=1]
[T=3]
[B=0]
[R=0]
[CB=0]
[CT=0]
[N=2]
[T=3]
[B=0]
[R=0]
[CB=0]
[CT=0]
[N=3]
[T=3]
[B=0]
[R=0]
[CB=0]
[CT=1]
[N=0]
[T=3]
[B=0]
[R=0]
[CB=0]
[CT=1]
[N=1]
[T=3]
[B=0]
[R=0]
[CB=0]
[CT=1]
[N=2]
[T=3]
[B=0]
[R=0]
[CB=0]
[CT=1]
[N=3]
[T=3]
[B=0]
[R=0]
[CB=0]
[CT=2]
[N=0]
[T=3]
[B=0]
[R=0]
[CB=0]
[CT=2]
[N=1]
[T=3]
[B=0]
[R=0]
[CB=0]
[CT=2]
[N=2]
[T=3]
[B=0]
[R=0]
[CB=0]
[CT=2]
[N=3]
[T=3]
[B=0]
[R=0]
[CB=1]
[CT=0]
[N=0]
[T=3]
[B=0]
[R=0]
[CB=1]
[CT=0]
[N=1]
R101
ct_coef
[T=3]
[B=0]
[R=0]
[CB=1]
[CT=0]
[N=2]
[T=3]
[B=0]
[R=0]
[CB=1]
[CT=0]
[N=3]
[T=3]
[B=0]
[R=0]
[CB=1]
[CT=1]
[N=0]
[T=3]
[B=0]
[R=0]
[CB=1]
[CT=1]
[N=1]
[T=3]
[B=0]
[R=0]
[CB=1]
[CT=1]
[N=2]
[T=3]
[B=0]
[R=0]
[CB=1]
[CT=1]
[N=3]
[T=3]
[B=0]
[R=0]
[CB=1]
[CT=2]
[N=0]
[T=3]
[B=0]
[R=0]
[CB=1]
[CT=2]
[N=1]
[T=3]
[B=0]
[R=0]
[CB=1]
[CT=2]
[N=2]
[T=3]
[B=0]
[R=0]
[CB=1]
[CT=2]
[N=3]
[T=3]
[B=0]
[R=0]
[CB=1]
[CT=3]
[N=0]
[T=3]
[B=0]
[R=0]
[CB=1]
[CT=3]
[N=1]
[T=3]
[B=0]
[R=0]
[CB=1]
[CT=3]
[N=2]
[T=3]
[B=0]
[R=0]
[CB=1]
[CT=3]
[N=3]
[T=3]
[B=0]
[R=0]
[CB=1]
[CT=4]
[N=0]
[T=3]
[B=0]
[R=0]
[CB=1]
[CT=4]
[N=1]
R102
ct_coef
[T=3]
[B=0]
[R=0]
[CB=1]
[CT=4]
[N=2]
[T=3]
[B=0]
[R=0]
[CB=1]
[CT=4]
[T=3]
[B=0]
[R=0]
[CB=1]
[CT=5]
[T=3]
[B=0]
[R=0]
[CB=1]
[CT=5]
[T=3]
[B=0]
[R=0]
[CB=1]
[CT=5]
[T=3]
[B=0]
[R=0]
[CB=1]
[CT=5]
[T=3]
[B=0]
[R=0]
[CB=2]
[CT=0]
[T=3]
[B=0]
[R=0]
[CB=2]
[CT=0]
[T=3]
[B=0]
[R=0]
[CB=2]
[CT=0]
[T=3]
[B=0]
[R=0]
[CB=2]
[CT=0]
[T=3]
[B=0]
[R=0]
[CB=2]
[CT=1]
[N=0]
[T=3]
[B=0]
[R=0]
[CB=2]
[CT=1]
[N=1]
[T=3]
[B=0]
[R=0]
[CB=2]
[CT=1]
[T=3]
[B=0]
[R=0]
[CB=2]
[CT=1]
[T=3]
[B=0]
[R=0]
[CB=2]
[CT=2]
[T=3]
[B=0]
[R=0]
[CB=2]
[CT=2]
[N=1]
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
33
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[N=3]
[N=0]
[N=1]
[N=2]
[N=3]
[N=0]
[N=1]
[N=2]
[N=3]
[N=2]
[N=3]
[N=0]
R103
ct_coef
[T=3]
[B=0]
[R=0]
[CB=2]
[CT=2]
[N=2]
[T=3]
[B=0]
[R=0]
[CB=2]
[CT=2]
[N=3]
[T=3]
[B=0]
[R=0]
[CB=2]
[CT=3]
[N=0]
[T=3]
[B=0]
[R=0]
[CB=2]
[CT=3]
[N=1]
[T=3]
[B=0]
[R=0]
[CB=2]
[CT=3]
[N=2]
[T=3]
[B=0]
[R=0]
[CB=2]
[CT=3]
[N=3]
[T=3]
[B=0]
[R=0]
[CB=2]
[CT=4]
[N=0]
[T=3]
[B=0]
[R=0]
[CB=2]
[CT=4]
[N=1]
[T=3]
[B=0]
[R=0]
[CB=2]
[CT=4]
[N=2]
[T=3]
[B=0]
[R=0]
[CB=2]
[CT=4]
[N=3]
[T=3]
[B=0]
[R=0]
[CB=2]
[CT=5]
[N=0]
[T=3]
[B=0]
[R=0]
[CB=2]
[CT=5]
[N=1]
[T=3]
[B=0]
[R=0]
[CB=2]
[CT=5]
[N=2]
[T=3]
[B=0]
[R=0]
[CB=2]
[CT=5]
[N=3]
[T=3]
[B=0]
[R=0]
[CB=3]
[CT=0]
[N=0]
[T=3]
[B=0]
[R=0]
[CB=3]
[CT=0]
[N=1]
R104
ct_coef
[T=3]
[B=0]
[R=0]
[CB=3]
[CT=0]
[N=2]
[T=3]
[B=0]
[R=0]
[CB=3]
[CT=0]
[N=3]
[T=3]
[B=0]
[R=0]
[CB=3]
[CT=1]
[N=0]
[T=3]
[B=0]
[R=0]
[CB=3]
[CT=1]
[N=1]
[T=3]
[B=0]
[R=0]
[CB=3]
[CT=1]
[N=2]
[T=3]
[B=0]
[R=0]
[CB=3]
[CT=1]
[N=3]
[T=3]
[B=0]
[R=0]
[CB=3]
[CT=2]
[N=0]
[T=3]
[B=0]
[R=0]
[CB=3]
[CT=2]
[N=1]
[T=3]
[B=0]
[R=0]
[CB=3]
[CT=2]
[N=2]
[T=3]
[B=0]
[R=0]
[CB=3]
[CT=2]
[N=3]
[T=3]
[B=0]
[R=0]
[CB=3]
[CT=3]
[N=0]
[T=3]
[B=0]
[R=0]
[CB=3]
[CT=3]
[N=1]
[T=3]
[B=0]
[R=0]
[CB=3]
[CT=3]
[N=2]
[T=3]
[B=0]
[R=0]
[CB=3]
[CT=3]
[N=3]
[T=3]
[B=0]
[R=0]
[CB=3]
[CT=4]
[N=0]
[T=3]
[B=0]
[R=0]
[CB=3]
[CT=4]
[N=1]
R105
ct_coef
[T=3]
[B=0]
[R=0]
[CB=3]
[CT=4]
[N=2]
[T=3]
[B=0]
[R=0]
[CB=3]
[CT=4]
[N=3]
[T=3]
[B=0]
[R=0]
[CB=3]
[CT=5]
[N=0]
[T=3]
[B=0]
[R=0]
[CB=3]
[CT=5]
[N=1]
[T=3]
[B=0]
[R=0]
[CB=3]
[CT=5]
[N=2]
[T=3]
[B=0]
[R=0]
[CB=3]
[CT=5]
[N=3]
[T=3]
[B=0]
[R=0]
[CB=4]
[CT=0]
[N=0]
[T=3]
[B=0]
[R=0]
[CB=4]
[CT=0]
[N=1]
[T=3]
[B=0]
[R=0]
[CB=4]
[CT=0]
[N=2]
[T=3]
[B=0]
[R=0]
[CB=4]
[CT=0]
[N=3]
[T=3]
[B=0]
[R=0]
[CB=4]
[CT=1]
[N=0]
[T=3]
[B=0]
[R=0]
[CB=4]
[CT=1]
[N=1]
[T=3]
[B=0]
[R=0]
[CB=4]
[CT=1]
[N=2]
[T=3]
[B=0]
[R=0]
[CB=4]
[CT=1]
[N=3]
[T=3]
[B=0]
[R=0]
[CB=4]
[CT=2]
[N=0]
[T=3]
[B=0]
[R=0]
[CB=4]
[CT=2]
[N=1]
R106
ct_coef
HEVC
34
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[T=3]
[B=0]
[R=0]
[CB=4]
[CT=2]
[N=2]
[T=3]
[B=0]
[R=0]
[CB=4]
[CT=2]
[N=3]
[T=3]
[B=0]
[R=0]
[CB=4]
[CT=3]
[N=0]
[T=3]
[B=0]
[R=0]
[CB=4]
[CT=3]
[N=1]
[T=3]
[B=0]
[R=0]
[CB=4]
[CT=3]
[N=2]
[T=3]
[B=0]
[R=0]
[CB=4]
[CT=3]
[N=3]
[T=3]
[B=0]
[R=0]
[CB=4]
[CT=4]
[N=0]
[T=3]
[B=0]
[R=0]
[CB=4]
[CT=4]
[N=1]
[T=3]
[B=0]
[R=0]
[CB=4]
[CT=4]
[N=2]
[T=3]
[B=0]
[R=0]
[CB=4]
[CT=4]
[N=3]
[T=3]
[B=0]
[R=0]
[CB=4]
[CT=5]
[N=0]
[T=3]
[B=0]
[R=0]
[CB=4]
[CT=5]
[N=1]
[T=3]
[B=0]
[R=0]
[CB=4]
[CT=5]
[N=2]
[T=3]
[B=0]
[R=0]
[CB=4]
[CT=5]
[N=3]
[T=3]
[B=0]
[R=0]
[CB=5]
[CT=0]
[N=0]
[T=3]
[B=0]
[R=0]
[CB=5]
[CT=0]
[N=1]
R107
ct_coef
[T=3]
[B=0]
[R=0]
[CB=5]
[CT=0]
[N=2]
[T=3]
[B=0]
[R=0]
[CB=5]
[CT=0]
[N=3]
[T=3]
[B=0]
[R=0]
[CB=5]
[CT=1]
[N=0]
[T=3]
[B=0]
[R=0]
[CB=5]
[CT=1]
[N=1]
[T=3]
[B=0]
[R=0]
[CB=5]
[CT=1]
[N=2]
[T=3]
[B=0]
[R=0]
[CB=5]
[CT=1]
[N=3]
[T=3]
[B=0]
[R=0]
[CB=5]
[CT=2]
[N=0]
[T=3]
[B=0]
[R=0]
[CB=5]
[CT=2]
[N=1]
[T=3]
[B=0]
[R=0]
[CB=5]
[CT=2]
[N=2]
[T=3]
[B=0]
[R=0]
[CB=5]
[CT=2]
[N=3]
[T=3]
[B=0]
[R=0]
[CB=5]
[CT=3]
[N=0]
[T=3]
[B=0]
[R=0]
[CB=5]
[CT=3]
[N=1]
[T=3]
[B=0]
[R=0]
[CB=5]
[CT=3]
[N=2]
[T=3]
[B=0]
[R=0]
[CB=5]
[CT=3]
[N=3]
[T=3]
[B=0]
[R=0]
[CB=5]
[CT=4]
[N=0]
[T=3]
[B=0]
[R=0]
[CB=5]
[CT=4]
[N=1]
R108
ct_coef
[T=3]
[B=0]
[R=0]
[CB=5]
[CT=4]
[N=2]
[T=3]
[B=0]
[R=0]
[CB=5]
[CT=4]
[N=3]
[T=3]
[B=0]
[R=0]
[CB=5]
[CT=5]
[N=0]
[T=3]
[B=0]
[R=0]
[CB=5]
[CT=5]
[N=1]
[T=3]
[B=0]
[R=0]
[CB=5]
[CT=5]
[N=2]
[T=3]
[B=0]
[R=0]
[CB=5]
[CT=5]
[N=3]
[T=3]
[B=0]
[R=1]
[CB=0]
[CT=0]
[N=0]
[T=3]
[B=0]
[R=1]
[CB=0]
[CT=0]
[N=1]
[T=3]
[B=0]
[R=1]
[CB=0]
[CT=0]
[N=2]
[T=3]
[B=0]
[R=1]
[CB=0]
[CT=0]
[N=3]
[T=3]
[B=0]
[R=1]
[CB=0]
[CT=1]
[N=0]
[T=3]
[B=0]
[R=1]
[CB=0]
[CT=1]
[N=1]
[T=3]
[B=0]
[R=1]
[CB=0]
[CT=1]
[N=2]
[T=3]
[B=0]
[R=1]
[CB=0]
[CT=1]
[N=3]
[T=3]
[B=0]
[R=1]
[CB=0]
[CT=2]
[N=0]
[T=3]
[B=0]
[R=1]
[CB=0]
[CT=2]
[N=1]
R109
ct_coef
[T=3]
[B=0]
[T=3]
[B=0]
[T=3]
[B=0]
[T=3]
[B=0]
[T=3]
[B=0]
[T=3]
[B=0]
[T=3]
[B=0]
[T=3]
[B=0]
[T=3]
[B=0]
[T=3]
[B=0]
[T=3]
[B=0]
[T=3]
[B=0]
[T=3]
[B=0]
[T=3]
[B=0]
[T=3]
[B=0]
[T=3]
[B=0]
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
35
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[R=1]
[CB=0]
[CT=2]
[N=2]
[R=1]
[CB=0]
[CT=2]
[N=3]
[R=1]
[CB=1]
[CT=0]
[N=0]
[R=1]
[CB=1]
[CT=0]
[N=1]
[R=1]
[CB=1]
[CT=0]
[N=2]
[R=1]
[CB=1]
[CT=0]
[N=3]
[R=1]
[CB=1]
[CT=1]
[N=0]
[R=1]
[CB=1]
[CT=1]
[N=1]
[R=1]
[CB=1]
[CT=1]
[N=2]
[R=1]
[CB=1]
[CT=1]
[N=3]
[R=1]
[CB=1]
[CT=2]
[N=0]
[R=1]
[CB=1]
[CT=2]
[N=1]
[R=1]
[CB=1]
[CT=2]
[N=2]
[R=1]
[CB=1]
[CT=2]
[N=3]
[R=1]
[CB=1]
[CT=3]
[N=0]
[R=1]
[CB=1]
[CT=3]
[N=1]
R110
ct_coef
[T=3]
[B=0]
[R=1]
[CB=1]
[CT=3]
[N=2]
[T=3]
[B=0]
[R=1]
[CB=1]
[CT=3]
[N=3]
[T=3]
[B=0]
[R=1]
[CB=1]
[CT=4]
[N=0]
[T=3]
[B=0]
[R=1]
[CB=1]
[CT=4]
[N=1]
[T=3]
[B=0]
[R=1]
[CB=1]
[CT=4]
[N=2]
[T=3]
[B=0]
[R=1]
[CB=1]
[CT=4]
[N=3]
[T=3]
[B=0]
[R=1]
[CB=1]
[CT=5]
[N=0]
[T=3]
[B=0]
[R=1]
[CB=1]
[CT=5]
[N=1]
[T=3]
[B=0]
[R=1]
[CB=1]
[CT=5]
[N=2]
[T=3]
[B=0]
[R=1]
[CB=1]
[CT=5]
[N=3]
[T=3]
[B=0]
[R=1]
[CB=2]
[CT=0]
[N=0]
[T=3]
[B=0]
[R=1]
[CB=2]
[CT=0]
[N=1]
[T=3]
[B=0]
[R=1]
[CB=2]
[CT=0]
[N=2]
[T=3]
[B=0]
[R=1]
[CB=2]
[CT=0]
[N=3]
[T=3]
[B=0]
[R=1]
[CB=2]
[CT=1]
[N=0]
[T=3]
[B=0]
[R=1]
[CB=2]
[CT=1]
[N=1]
R111
ct_coef
[T=3]
[B=0]
[R=1]
[CB=2]
[CT=1]
[N=2]
[T=3]
[B=0]
[R=1]
[CB=2]
[CT=1]
[N=3]
[T=3]
[B=0]
[R=1]
[CB=2]
[CT=2]
[N=0]
[T=3]
[B=0]
[R=1]
[CB=2]
[CT=2]
[N=1]
[T=3]
[B=0]
[R=1]
[CB=2]
[CT=2]
[N=2]
[T=3]
[B=0]
[R=1]
[CB=2]
[CT=2]
[N=3]
[T=3]
[B=0]
[R=1]
[CB=2]
[CT=3]
[N=0]
[T=3]
[B=0]
[R=1]
[CB=2]
[CT=3]
[N=1]
[T=3]
[B=0]
[R=1]
[CB=2]
[CT=3]
[N=2]
[T=3]
[B=0]
[R=1]
[CB=2]
[CT=3]
[N=3]
[T=3]
[B=0]
[R=1]
[CB=2]
[CT=4]
[N=0]
[T=3]
[B=0]
[R=1]
[CB=2]
[CT=4]
[N=1]
[T=3]
[B=0]
[R=1]
[CB=2]
[CT=4]
[N=2]
[T=3]
[B=0]
[R=1]
[CB=2]
[CT=4]
[N=3]
[T=3]
[B=0]
[R=1]
[CB=2]
[CT=5]
[N=0]
[T=3]
[B=0]
[R=1]
[CB=2]
[CT=5]
[N=1]
R112
ct_coef
[T=3]
[B=0]
[R=1]
[CB=2]
[T=3]
[B=0]
[R=1]
[T=3]
[B=0]
[R=1]
[T=3]
[B=0]
[R=1]
[T=3]
[B=0]
[R=1]
[T=3]
[B=0]
[R=1]
[T=3]
[B=0]
[R=1]
[T=3]
[B=0]
[R=1]
[T=3]
[B=0]
[R=1]
[T=3]
[B=0]
[R=1]
[T=3]
[B=0]
[R=1]
[T=3]
[B=0]
[R=1]
[T=3]
[B=0]
[R=1]
[T=3]
[B=0]
[R=1]
[T=3]
[B=0]
[R=1]
[T=3]
[B=0]
[R=1]
[CB=3]
HEVC
36
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[CT=5]
[N=2]
[CB=2]
[CT=5]
[N=3]
[CB=3]
[CT=0]
[N=0]
[CB=3]
[CT=0]
[N=1]
[CB=3]
[CT=0]
[N=2]
[CB=3]
[CT=0]
[N=3]
[CB=3]
[CT=1]
[N=0]
[CB=3]
[CT=1]
[N=1]
[CB=3]
[CT=1]
[N=2]
[CB=3]
[CT=1]
[N=3]
[CB=3]
[CT=2]
[N=0]
[CB=3]
[CT=2]
[N=1]
[CB=3]
[CT=2]
[N=2]
[CB=3]
[CT=2]
[N=3]
[CB=3]
[CT=3]
[N=0]
[CT=3]
[N=1]
R113
ct_coef
[T=3]
[B=0]
[R=1]
[CB=3]
[CT=3]
[N=2]
[T=3]
[B=0]
[R=1]
[CB=3]
[CT=3]
[N=3]
[T=3]
[B=0]
[R=1]
[CB=3]
[CT=4]
[N=0]
[T=3]
[B=0]
[R=1]
[CB=3]
[CT=4]
[N=1]
[T=3]
[B=0]
[R=1]
[CB=3]
[CT=4]
[N=2]
[T=3]
[B=0]
[R=1]
[CB=3]
[CT=4]
[N=3]
[T=3]
[B=0]
[R=1]
[CB=3]
[CT=5]
[N=0]
[T=3]
[B=0]
[R=1]
[CB=3]
[CT=5]
[N=1]
[T=3]
[B=0]
[R=1]
[CB=3]
[CT=5]
[N=2]
[T=3]
[B=0]
[R=1]
[CB=3]
[CT=5]
[N=3]
[T=3]
[B=0]
[R=1]
[CB=4]
[CT=0]
[N=0]
[T=3]
[B=0]
[R=1]
[CB=4]
[CT=0]
[N=1]
[T=3]
[B=0]
[R=1]
[CB=4]
[CT=0]
[N=2]
[T=3]
[B=0]
[R=1]
[CB=4]
[CT=0]
[N=3]
[T=3]
[B=0]
[R=1]
[CB=4]
[CT=1]
[N=0]
[T=3]
[B=0]
[R=1]
[CB=4]
[CT=1]
[N=1]
R114
ct_coef
[T=3]
[B=0]
[R=1]
[CB=4]
[CT=1]
[N=2]
[T=3]
[B=0]
[R=1]
[CB=4]
[CT=1]
[N=3]
[T=3]
[B=0]
[R=1]
[CB=4]
[CT=2]
[N=0]
[T=3]
[B=0]
[R=1]
[CB=4]
[CT=2]
[N=1]
[T=3]
[B=0]
[R=1]
[CB=4]
[CT=2]
[N=2]
[T=3]
[B=0]
[R=1]
[CB=4]
[CT=2]
[N=3]
[T=3]
[B=0]
[R=1]
[CB=4]
[CT=3]
[N=0]
[T=3]
[B=0]
[R=1]
[CB=4]
[CT=3]
[N=1]
[T=3]
[B=0]
[R=1]
[CB=4]
[CT=3]
[N=2]
[T=3]
[B=0]
[R=1]
[CB=4]
[CT=3]
[N=3]
[T=3]
[B=0]
[R=1]
[CB=4]
[CT=4]
[N=0]
[T=3]
[B=0]
[R=1]
[CB=4]
[CT=4]
[N=1]
[T=3]
[B=0]
[R=1]
[CB=4]
[CT=4]
[N=2]
[T=3]
[B=0]
[R=1]
[CB=4]
[CT=4]
[N=3]
[T=3]
[B=0]
[R=1]
[CB=4]
[CT=5]
[N=0]
[T=3]
[B=0]
[R=1]
[CB=4]
[CT=5]
[N=1]
R115
ct_coef
[T=3]
[B=0]
[R=1]
[CB=4]
[CT=5]
[N=2]
[T=3]
[B=0]
[R=1]
[CB=4]
[T=3]
[B=0]
[R=1]
[CB=5]
[T=3]
[B=0]
[R=1]
[CB=5]
[T=3]
[B=0]
[R=1]
[CB=5]
[T=3]
[B=0]
[R=1]
[CB=5]
[T=3]
[B=0]
[R=1]
[CB=5]
[T=3]
[B=0]
[R=1]
[CB=5]
[T=3]
[B=0]
[R=1]
[CB=5]
[T=3]
[B=0]
[R=1]
[CB=5]
[T=3]
[B=0]
[R=1]
[CB=5]
[CT=2]
[T=3]
[B=0]
[R=1]
[CB=5]
[CT=2]
[T=3]
[B=0]
[R=1]
[CB=5]
[T=3]
[B=0]
[R=1]
[CB=5]
[T=3]
[B=0]
[R=1]
[CB=5]
[T=3]
[B=0]
[R=1]
[CB=5]
[CT=3]
[N=1]
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
37
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[CT=5]
[N=3]
[CT=0]
[N=0]
[CT=0]
[N=1]
[CT=0]
[N=2]
[CT=0]
[N=3]
[CT=1]
[N=0]
[CT=1]
[N=1]
[CT=1]
[N=2]
[CT=1]
[N=3]
[N=0]
[N=1]
[CT=2]
[N=2]
[CT=2]
[N=3]
[CT=3]
[N=0]
R116
ct_coef
[T=3]
[B=0]
[R=1]
[CB=5]
[CT=3]
[N=2]
[T=3]
[B=0]
[R=1]
[CB=5]
[CT=3]
[N=3]
[T=3]
[B=0]
[R=1]
[CB=5]
[CT=4]
[N=0]
[T=3]
[B=0]
[R=1]
[CB=5]
[CT=4]
[N=1]
[T=3]
[B=0]
[R=1]
[CB=5]
[CT=4]
[N=2]
[T=3]
[B=0]
[R=1]
[CB=5]
[CT=4]
[N=3]
[T=3]
[B=0]
[R=1]
[CB=5]
[CT=5]
[N=0]
[T=3]
[B=0]
[R=1]
[CB=5]
[CT=5]
[N=1]
[T=3]
[B=0]
[R=1]
[CB=5]
[CT=5]
[N=2]
[T=3]
[B=0]
[R=1]
[CB=5]
[CT=5]
[N=3]
[T=3]
[B=1]
[R=0]
[CB=0]
[CT=0]
[N=0]
[T=3]
[B=1]
[R=0]
[CB=0]
[CT=0]
[N=1]
[T=3]
[B=1]
[R=0]
[CB=0]
[CT=0]
[N=2]
[T=3]
[B=1]
[R=0]
[CB=0]
[CT=0]
[N=3]
[T=3]
[B=1]
[R=0]
[CB=0]
[CT=1]
[N=0]
[T=3]
[B=1]
[R=0]
[CB=0]
[CT=1]
[N=1]
R117
ct_coef
[T=3]
[B=1]
[R=0]
[CB=0]
[CT=1]
[N=2]
[T=3]
[B=1]
[R=0]
[CB=0]
[CT=1]
[N=3]
[T=3]
[B=1]
[R=0]
[CB=0]
[CT=2]
[N=0]
[T=3]
[B=1]
[R=0]
[CB=0]
[CT=2]
[N=1]
[T=3]
[B=1]
[R=0]
[CB=0]
[CT=2]
[N=2]
[T=3]
[B=1]
[R=0]
[CB=0]
[CT=2]
[N=3]
[T=3]
[B=1]
[R=0]
[CB=1]
[CT=0]
[N=0]
[T=3]
[B=1]
[R=0]
[CB=1]
[CT=0]
[N=1]
[T=3]
[B=1]
[R=0]
[CB=1]
[CT=0]
[N=2]
[T=3]
[B=1]
[R=0]
[CB=1]
[CT=0]
[N=3]
[T=3]
[B=1]
[R=0]
[CB=1]
[CT=1]
[N=0]
[T=3]
[B=1]
[R=0]
[CB=1]
[CT=1]
[N=1]
[T=3]
[B=1]
[R=0]
[CB=1]
[CT=1]
[N=2]
[T=3]
[B=1]
[R=0]
[CB=1]
[CT=1]
[N=3]
[T=3]
[B=1]
[R=0]
[CB=1]
[CT=2]
[N=0]
[T=3]
[B=1]
[R=0]
[CB=1]
[CT=2]
[N=1]
R118
ct_coef
[T=3]
[B=1]
[R=0]
[CB=1]
[CT=2]
[N=2]
[T=3]
[B=1]
[R=0]
[CB=1]
[CT=2]
[N=3]
[T=3]
[B=1]
[R=0]
[CB=1]
[CT=3]
[N=0]
[T=3]
[B=1]
[R=0]
[CB=1]
[CT=3]
[N=1]
[T=3]
[B=1]
[R=0]
[CB=1]
[CT=3]
[N=2]
[T=3]
[B=1]
[R=0]
[CB=1]
[CT=3]
[N=3]
[T=3]
[B=1]
[R=0]
[CB=1]
[CT=4]
[N=0]
[T=3]
[B=1]
[R=0]
[CB=1]
[CT=4]
[N=1]
[T=3]
[B=1]
[R=0]
[CB=1]
[CT=4]
[N=2]
[T=3]
[B=1]
[R=0]
[CB=1]
[CT=4]
[N=3]
[T=3]
[B=1]
[R=0]
[CB=1]
[CT=5]
[N=0]
[T=3]
[B=1]
[R=0]
[CB=1]
[CT=5]
[N=1]
[T=3]
[B=1]
[R=0]
[CB=1]
[CT=5]
[N=2]
[T=3]
[B=1]
[R=0]
[CB=1]
[CT=5]
[N=3]
[T=3]
[B=1]
[R=0]
[CB=2]
[CT=0]
[N=0]
[T=3]
[B=1]
[R=0]
[CB=2]
[CT=0]
[N=1]
HEVC
38
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R119
ct_coef
[T=3]
[B=1]
[R=0]
[CB=2]
[CT=0]
[N=2]
[T=3]
[B=1]
[R=0]
[CB=2]
[CT=0]
[N=3]
[T=3]
[B=1]
[R=0]
[CB=2]
[CT=1]
[N=0]
[T=3]
[B=1]
[R=0]
[CB=2]
[CT=1]
[N=1]
[T=3]
[B=1]
[R=0]
[CB=2]
[CT=1]
[N=2]
[T=3]
[B=1]
[R=0]
[CB=2]
[CT=1]
[N=3]
[T=3]
[B=1]
[R=0]
[CB=2]
[CT=2]
[N=0]
[T=3]
[B=1]
[R=0]
[CB=2]
[CT=2]
[N=1]
[T=3]
[B=1]
[R=0]
[CB=2]
[CT=2]
[N=2]
[T=3]
[B=1]
[R=0]
[CB=2]
[CT=2]
[N=3]
[T=3]
[B=1]
[R=0]
[CB=2]
[CT=3]
[N=0]
[T=3]
[B=1]
[R=0]
[CB=2]
[CT=3]
[N=1]
[T=3]
[B=1]
[R=0]
[CB=2]
[CT=3]
[N=2]
[T=3]
[B=1]
[R=0]
[CB=2]
[CT=3]
[N=3]
[T=3]
[B=1]
[R=0]
[CB=2]
[CT=4]
[N=0]
[T=3]
[B=1]
[R=0]
[CB=2]
[CT=4]
[N=1]
R120
ct_coef
[T=3]
[B=1]
[R=0]
[CB=2]
[CT=4]
[N=2]
[T=3]
[B=1]
[R=0]
[CB=2]
[CT=4]
[N=3]
[T=3]
[B=1]
[R=0]
[CB=2]
[CT=5]
[N=0]
[T=3]
[B=1]
[R=0]
[CB=2]
[CT=5]
[N=1]
[T=3]
[B=1]
[R=0]
[CB=2]
[CT=5]
[N=2]
[T=3]
[B=1]
[R=0]
[CB=2]
[CT=5]
[N=3]
[T=3]
[B=1]
[R=0]
[CB=3]
[CT=0]
[N=0]
[T=3]
[B=1]
[R=0]
[CB=3]
[CT=0]
[N=1]
[T=3]
[B=1]
[R=0]
[CB=3]
[CT=0]
[N=2]
[T=3]
[B=1]
[R=0]
[CB=3]
[CT=0]
[N=3]
[T=3]
[B=1]
[R=0]
[CB=3]
[CT=1]
[N=0]
[T=3]
[B=1]
[R=0]
[CB=3]
[CT=1]
[N=1]
[T=3]
[B=1]
[R=0]
[CB=3]
[CT=1]
[N=2]
[T=3]
[B=1]
[R=0]
[CB=3]
[CT=1]
[N=3]
[T=3]
[B=1]
[R=0]
[CB=3]
[CT=2]
[N=0]
[T=3]
[B=1]
[R=0]
[CB=3]
[CT=2]
[N=1]
R121
ct_coef
[T=3]
[B=1]
[R=0]
[CB=3]
[CT=2]
[N=2]
[T=3]
[B=1]
[R=0]
[CB=3]
[CT=2]
[N=3]
[T=3]
[B=1]
[R=0]
[CB=3]
[CT=3]
[N=0]
[T=3]
[B=1]
[R=0]
[CB=3]
[CT=3]
[N=1]
[T=3]
[B=1]
[R=0]
[CB=3]
[CT=3]
[N=2]
[T=3]
[B=1]
[R=0]
[CB=3]
[CT=3]
[N=3]
[T=3]
[B=1]
[R=0]
[CB=3]
[CT=4]
[N=0]
[T=3]
[B=1]
[R=0]
[CB=3]
[CT=4]
[N=1]
[T=3]
[B=1]
[R=0]
[CB=3]
[CT=4]
[N=2]
[T=3]
[B=1]
[R=0]
[CB=3]
[CT=4]
[N=3]
[T=3]
[B=1]
[R=0]
[CB=3]
[CT=5]
[N=0]
[T=3]
[B=1]
[R=0]
[CB=3]
[CT=5]
[N=1]
[T=3]
[B=1]
[R=0]
[CB=3]
[CT=5]
[N=2]
[T=3]
[B=1]
[R=0]
[CB=3]
[CT=5]
[N=3]
[T=3]
[B=1]
[R=0]
[CB=4]
[CT=0]
[N=0]
[T=3]
[B=1]
[R=0]
[CB=4]
[CT=0]
[N=1]
R122
ct_coef
[T=3]
[T=3]
[T=3]
[T=3]
[T=3]
[T=3]
[T=3]
[T=3]
[T=3]
[T=3]
[T=3]
[T=3]
[T=3]
[T=3]
[T=3]
[T=3]
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
39
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[B=1]
[R=0]
[CB=4]
[CT=0]
[N=2]
[B=1]
[R=0]
[CB=4]
[CT=0]
[N=3]
[B=1]
[R=0]
[CB=4]
[CT=1]
[N=0]
[B=1]
[R=0]
[CB=4]
[CT=1]
[N=1]
[B=1]
[R=0]
[CB=4]
[CT=1]
[N=2]
[B=1]
[R=0]
[CB=4]
[CT=1]
[N=3]
[B=1]
[R=0]
[CB=4]
[CT=2]
[N=0]
[B=1]
[R=0]
[CB=4]
[CT=2]
[N=1]
[B=1]
[R=0]
[CB=4]
[CT=2]
[N=2]
[B=1]
[R=0]
[CB=4]
[CT=2]
[N=3]
[B=1]
[R=0]
[CB=4]
[CT=3]
[N=0]
[B=1]
[R=0]
[CB=4]
[CT=3]
[N=1]
[B=1]
[R=0]
[CB=4]
[CT=3]
[N=2]
[B=1]
[R=0]
[CB=4]
[CT=3]
[N=3]
[B=1]
[R=0]
[CB=4]
[CT=4]
[N=0]
[B=1]
[R=0]
[CB=4]
[CT=4]
[N=1]
R123
ct_coef
[T=3]
[B=1]
[R=0]
[CB=4]
[CT=4]
[N=2]
[T=3]
[B=1]
[R=0]
[CB=4]
[CT=4]
[N=3]
[T=3]
[B=1]
[R=0]
[CB=4]
[CT=5]
[N=0]
[T=3]
[B=1]
[R=0]
[CB=4]
[CT=5]
[N=1]
[T=3]
[B=1]
[R=0]
[CB=4]
[CT=5]
[N=2]
[T=3]
[B=1]
[R=0]
[CB=4]
[CT=5]
[N=3]
[T=3]
[B=1]
[R=0]
[CB=5]
[CT=0]
[N=0]
[T=3]
[B=1]
[R=0]
[CB=5]
[CT=0]
[N=1]
[T=3]
[B=1]
[R=0]
[CB=5]
[CT=0]
[N=2]
[T=3]
[B=1]
[R=0]
[CB=5]
[CT=0]
[N=3]
[T=3]
[B=1]
[R=0]
[CB=5]
[CT=1]
[N=0]
[T=3]
[B=1]
[R=0]
[CB=5]
[CT=1]
[N=1]
[T=3]
[B=1]
[R=0]
[CB=5]
[CT=1]
[N=2]
[T=3]
[B=1]
[R=0]
[CB=5]
[CT=1]
[N=3]
[T=3]
[B=1]
[R=0]
[CB=5]
[CT=2]
[N=0]
[T=3]
[B=1]
[R=0]
[CB=5]
[CT=2]
[N=1]
R124
ct_coef
[T=3]
[B=1]
[R=0]
[CB=5]
[CT=2]
[N=2]
[T=3]
[B=1]
[R=0]
[CB=5]
[CT=2]
[N=3]
[T=3]
[B=1]
[R=0]
[CB=5]
[CT=3]
[N=0]
[T=3]
[B=1]
[R=0]
[CB=5]
[CT=3]
[N=1]
[T=3]
[B=1]
[R=0]
[CB=5]
[CT=3]
[N=2]
[T=3]
[B=1]
[R=0]
[CB=5]
[CT=3]
[N=3]
[T=3]
[B=1]
[R=0]
[CB=5]
[CT=4]
[N=0]
[T=3]
[B=1]
[R=0]
[CB=5]
[CT=4]
[N=1]
[T=3]
[B=1]
[R=0]
[CB=5]
[CT=4]
[N=2]
[T=3]
[B=1]
[R=0]
[CB=5]
[CT=4]
[N=3]
[T=3]
[B=1]
[R=0]
[CB=5]
[CT=5]
[N=0]
[T=3]
[B=1]
[R=0]
[CB=5]
[CT=5]
[N=1]
[T=3]
[B=1]
[R=0]
[CB=5]
[CT=5]
[N=2]
[T=3]
[B=1]
[R=0]
[CB=5]
[CT=5]
[N=3]
[T=3]
[B=1]
[R=1]
[CB=0]
[CT=0]
[N=0]
[T=3]
[B=1]
[R=1]
[CB=0]
[CT=0]
[N=1]
R125
ct_coef
[T=3]
[B=1]
[R=1]
[T=3]
[B=1]
[R=1]
[T=3]
[B=1]
[R=1]
[T=3]
[B=1]
[R=1]
[T=3]
[B=1]
[R=1]
[T=3]
[B=1]
[R=1]
[T=3]
[B=1]
[R=1]
[T=3]
[B=1]
[R=1]
[T=3]
[B=1]
[R=1]
[T=3]
[B=1]
[R=1]
[T=3]
[B=1]
[R=1]
[T=3]
[B=1]
[R=1]
[T=3]
[B=1]
[R=1]
[T=3]
[B=1]
[R=1]
[T=3]
[B=1]
[R=1]
[T=3]
[B=1]
[R=1]
HEVC
40
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[CB=0]
[CT=0]
[N=2]
[CB=0]
[CT=0]
[N=3]
[CB=0]
[CT=1]
[N=0]
[CB=0]
[CT=1]
[N=1]
[CB=0]
[CT=1]
[N=2]
[CB=0]
[CT=1]
[N=3]
[CB=0]
[CT=2]
[N=0]
[CB=0]
[CT=2]
[N=1]
[CB=0]
[CT=2]
[N=2]
[CB=0]
[CT=2]
[N=3]
[CB=1]
[CT=0]
[N=0]
[CB=1]
[CT=0]
[N=1]
[CB=1]
[CT=0]
[N=2]
[CB=1]
[CT=0]
[N=3]
[CB=1]
[CT=1]
[N=0]
[CB=1]
[CT=1]
[N=1]
R126
ct_coef
[T=3]
[B=1]
[R=1]
[CB=1]
[CT=1]
[N=2]
[T=3]
[B=1]
[R=1]
[CB=1]
[CT=1]
[N=3]
[T=3]
[B=1]
[R=1]
[CB=1]
[CT=2]
[N=0]
[T=3]
[B=1]
[R=1]
[CB=1]
[CT=2]
[N=1]
[T=3]
[B=1]
[R=1]
[CB=1]
[CT=2]
[N=2]
[T=3]
[B=1]
[R=1]
[CB=1]
[CT=2]
[N=3]
[T=3]
[B=1]
[R=1]
[CB=1]
[CT=3]
[N=0]
[T=3]
[B=1]
[R=1]
[CB=1]
[CT=3]
[N=1]
[T=3]
[B=1]
[R=1]
[CB=1]
[CT=3]
[N=2]
[T=3]
[B=1]
[R=1]
[CB=1]
[CT=3]
[N=3]
[T=3]
[B=1]
[R=1]
[CB=1]
[CT=4]
[N=0]
[T=3]
[B=1]
[R=1]
[CB=1]
[CT=4]
[N=1]
[T=3]
[B=1]
[R=1]
[CB=1]
[CT=4]
[N=2]
[T=3]
[B=1]
[R=1]
[CB=1]
[CT=4]
[N=3]
[T=3]
[B=1]
[R=1]
[CB=1]
[CT=5]
[N=0]
[T=3]
[B=1]
[R=1]
[CB=1]
[CT=5]
[N=1]
R127
ct_coef
[T=3]
[B=1]
[R=1]
[CB=1]
[CT=5]
[N=2]
[T=3]
[B=1]
[R=1]
[CB=1]
[CT=5]
[N=3]
[T=3]
[B=1]
[R=1]
[CB=2]
[CT=0]
[N=0]
[T=3]
[B=1]
[R=1]
[CB=2]
[CT=0]
[N=1]
[T=3]
[B=1]
[R=1]
[CB=2]
[CT=0]
[N=2]
[T=3]
[B=1]
[R=1]
[CB=2]
[CT=0]
[N=3]
[T=3]
[B=1]
[R=1]
[CB=2]
[CT=1]
[N=0]
[T=3]
[B=1]
[R=1]
[CB=2]
[CT=1]
[N=1]
[T=3]
[B=1]
[R=1]
[CB=2]
[CT=1]
[N=2]
[T=3]
[B=1]
[R=1]
[CB=2]
[CT=1]
[N=3]
[T=3]
[B=1]
[R=1]
[CB=2]
[CT=2]
[N=0]
[T=3]
[B=1]
[R=1]
[CB=2]
[CT=2]
[N=1]
[T=3]
[B=1]
[R=1]
[CB=2]
[CT=2]
[N=2]
[T=3]
[B=1]
[R=1]
[CB=2]
[CT=2]
[N=3]
[T=3]
[B=1]
[R=1]
[CB=2]
[CT=3]
[N=0]
[T=3]
[B=1]
[R=1]
[CB=2]
[CT=3]
[N=1]
R128
ct_coef
[T=3]
[B=1]
[R=1]
[CB=2]
[CT=3]
[T=3]
[B=1]
[R=1]
[CB=2]
[T=3]
[B=1]
[R=1]
[CB=2]
[T=3]
[B=1]
[R=1]
[CB=2]
[T=3]
[B=1]
[R=1]
[CB=2]
[T=3]
[B=1]
[R=1]
[CB=2]
[T=3]
[B=1]
[R=1]
[CB=2]
[T=3]
[B=1]
[R=1]
[CB=2]
[T=3]
[B=1]
[R=1]
[CB=2]
[T=3]
[B=1]
[R=1]
[CB=2]
[T=3]
[B=1]
[R=1]
[CB=3]
[T=3]
[B=1]
[R=1]
[CB=3]
[T=3]
[B=1]
[R=1]
[CB=3]
[T=3]
[B=1]
[R=1]
[CB=3]
[T=3]
[B=1]
[R=1]
[CB=3]
[T=3]
[B=1]
[R=1]
[CB=3]
[CT=1]
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
41
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[N=2]
[CT=3]
[N=3]
[CT=4]
[N=0]
[CT=4]
[N=1]
[CT=4]
[N=2]
[CT=4]
[N=3]
[CT=5]
[N=0]
[CT=5]
[N=1]
[CT=5]
[N=2]
[CT=5]
[N=3]
[CT=0]
[N=0]
[CT=0]
[N=1]
[CT=0]
[N=2]
[CT=0]
[N=3]
[CT=1]
[N=0]
[N=1]
R129
ct_coef
[T=3]
[B=1]
[R=1]
[CB=3]
[CT=1]
[N=2]
[T=3]
[B=1]
[R=1]
[CB=3]
[CT=1]
[N=3]
[T=3]
[B=1]
[R=1]
[CB=3]
[CT=2]
[N=0]
[T=3]
[B=1]
[R=1]
[CB=3]
[CT=2]
[N=1]
[T=3]
[B=1]
[R=1]
[CB=3]
[CT=2]
[N=2]
[T=3]
[B=1]
[R=1]
[CB=3]
[CT=2]
[N=3]
[T=3]
[B=1]
[R=1]
[CB=3]
[CT=3]
[N=0]
[T=3]
[B=1]
[R=1]
[CB=3]
[CT=3]
[N=1]
[T=3]
[B=1]
[R=1]
[CB=3]
[CT=3]
[N=2]
[T=3]
[B=1]
[R=1]
[CB=3]
[CT=3]
[N=3]
[T=3]
[B=1]
[R=1]
[CB=3]
[CT=4]
[N=0]
[T=3]
[B=1]
[R=1]
[CB=3]
[CT=4]
[N=1]
[T=3]
[B=1]
[R=1]
[CB=3]
[CT=4]
[N=2]
[T=3]
[B=1]
[R=1]
[CB=3]
[CT=4]
[N=3]
[T=3]
[B=1]
[R=1]
[CB=3]
[CT=5]
[N=0]
[T=3]
[B=1]
[R=1]
[CB=3]
[CT=5]
[N=1]
R130
ct_coef
[T=3]
[B=1]
[R=1]
[CB=3]
[CT=5]
[N=2]
[T=3]
[B=1]
[R=1]
[CB=3]
[CT=5]
[N=3]
[T=3]
[B=1]
[R=1]
[CB=4]
[CT=0]
[N=0]
[T=3]
[B=1]
[R=1]
[CB=4]
[CT=0]
[N=1]
[T=3]
[B=1]
[R=1]
[CB=4]
[CT=0]
[N=2]
[T=3]
[B=1]
[R=1]
[CB=4]
[CT=0]
[N=3]
[T=3]
[B=1]
[R=1]
[CB=4]
[CT=1]
[N=0]
[T=3]
[B=1]
[R=1]
[CB=4]
[CT=1]
[N=1]
[T=3]
[B=1]
[R=1]
[CB=4]
[CT=1]
[N=2]
[T=3]
[B=1]
[R=1]
[CB=4]
[CT=1]
[N=3]
[T=3]
[B=1]
[R=1]
[CB=4]
[CT=2]
[N=0]
[T=3]
[B=1]
[R=1]
[CB=4]
[CT=2]
[N=1]
[T=3]
[B=1]
[R=1]
[CB=4]
[CT=2]
[N=2]
[T=3]
[B=1]
[R=1]
[CB=4]
[CT=2]
[N=3]
[T=3]
[B=1]
[R=1]
[CB=4]
[CT=3]
[N=0]
[T=3]
[B=1]
[R=1]
[CB=4]
[CT=3]
[N=1]
R131
ct_coef
[T=3]
[B=1]
[R=1]
[CB=4]
[CT=3]
[N=2]
[T=3]
[B=1]
[R=1]
[CB=4]
[CT=3]
[T=3]
[B=1]
[R=1]
[CB=4]
[CT=4]
[T=3]
[B=1]
[R=1]
[CB=4]
[CT=4]
[T=3]
[B=1]
[R=1]
[CB=4]
[CT=4]
[T=3]
[B=1]
[R=1]
[CB=4]
[CT=4]
[T=3]
[B=1]
[R=1]
[CB=4]
[CT=5]
[T=3]
[B=1]
[R=1]
[CB=4]
[CT=5]
[T=3]
[B=1]
[R=1]
[CB=4]
[CT=5]
[T=3]
[B=1]
[R=1]
[CB=4]
[CT=5]
[T=3]
[B=1]
[R=1]
[CB=5]
[CT=0]
[N=0]
[T=3]
[B=1]
[R=1]
[CB=5]
[CT=0]
[N=1]
[T=3]
[B=1]
[R=1]
[CB=5]
[CT=0]
[T=3]
[B=1]
[R=1]
[CB=5]
[CT=0]
[T=3]
[B=1]
[R=1]
[CB=5]
[CT=1]
[T=3]
[B=1]
[R=1]
[CB=5]
[CT=1]
[N=1]
HEVC
42
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[N=3]
[N=0]
[N=1]
[N=2]
[N=3]
[N=0]
[N=1]
[N=2]
[N=3]
[N=2]
[N=3]
[N=0]
R132
ct_coef
[T=3]
[B=1]
[R=1]
[CB=5]
[CT=1]
[N=2]
[T=3]
[B=1]
[R=1]
[CB=5]
[CT=1]
[N=3]
[T=3]
[B=1]
[R=1]
[CB=5]
[CT=2]
[N=0]
[T=3]
[B=1]
[R=1]
[CB=5]
[CT=2]
[N=1]
[T=3]
[B=1]
[R=1]
[CB=5]
[CT=2]
[N=2]
[T=3]
[B=1]
[R=1]
[CB=5]
[CT=2]
[N=3]
[T=3]
[B=1]
[R=1]
[CB=5]
[CT=3]
[N=0]
[T=3]
[B=1]
[R=1]
[CB=5]
[CT=3]
[N=1]
[T=3]
[B=1]
[R=1]
[CB=5]
[CT=3]
[N=2]
[T=3]
[B=1]
[R=1]
[CB=5]
[CT=3]
[N=3]
[T=3]
[B=1]
[R=1]
[CB=5]
[CT=4]
[N=0]
[T=3]
[B=1]
[R=1]
[CB=5]
[CT=4]
[N=1]
[T=3]
[B=1]
[R=1]
[CB=5]
[CT=4]
[N=2]
[T=3]
[B=1]
[R=1]
[CB=5]
[CT=4]
[N=3]
[T=3]
[B=1]
[R=1]
[CB=5]
[CT=5]
[N=0]
[T=3]
[B=1]
[R=1]
[CB=5]
[CT=5]
[N=1]
R133
ct_coef
ct_mbskip
ct_inter_mode
[T=3]
[B=1]
[R=1]
[CB=5]
[CT=5]
[N=2]
[T=3]
[B=1]
[R=1]
[CB=5]
[CT=5]
[N=3]
[0]
[0]
[0]
[1]
[1]
[0]
[1]
[1]
[2]
[0]
[2]
[1]
[0]
[0]
[0]
[1]
[0]
[2]
[0]
[3]
[1]
[0]
[1]
[1]
[1]
[2]
[1]
[3]
R134
ct_inter_mode
[2]
[0]
[2]
[1]
[2]
[2]
[2]
[3]
[3]
[0]
[3]
[1]
[3]
[2]
[3]
[3]
[4]
[0]
[4]
[1]
[4]
[2]
[4]
[3]
[5]
[0]
[5]
[1]
[5]
[2]
[5]
[3]
R135
ct_inter_mode
ct_switchable_interp
[6]
[0]
[6]
[1]
[6]
[2]
[6]
[3]
[0]
[0]
[0]
[1]
[0]
[2]
[1]
[0]
[1]
[1]
[1]
[2]
[2]
[0]
[2]
[1]
[2]
[2]
[3]
[0]
[3]
[1]
[3]
[2]
R136
ct_intra_inter
ct_comp_inter
[0]
[0]
[0]
[1]
[1]
[0]
[1]
[1]
[2]
[0]
[2]
[1]
[3]
[0]
[3]
[1]
[0]
[0]
[0]
[1]
[1]
[0]
[1]
[1]
[2]
[0]
[2]
[1]
[3]
[0]
[3]
[1]
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
43
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R137
ct_comp_inter
ct_single_ref
[4]
[0]
[4]
[1]
[0]
[0]
[0]
[0]
[0]
[1]
[0]
[1]
[0]
[0]
[1]
[1]
[1]
[0]
[0]
[1]
[0]
[1]
[1]
[1]
[0]
[1]
[1]
[1]
[2]
[0]
[0]
[2]
[0]
[1]
[2]
[1]
[0]
[2]
[1]
[1]
[3]
[0]
[0]
[3]
[0]
[1]
R138
ct_single_ref
ct_comp_ref
[3]
[1]
[0]
[3]
[1]
[1]
[4]
[0]
[0]
[4]
[0]
[1]
[4]
[1]
[0]
[4]
[1]
[1]
[0]
[0]
[0]
[1]
[1]
[0]
[1]
[1]
[2]
[0]
[2]
[1]
[3]
[0]
[3]
[1]
[4]
[0]
[4]
[1]
R139
ct_y_mode
[0]
[0]
[0]
[1]
[0]
[2]
[0]
[3]
[0]
[4]
[0]
[5]
[0]
[6]
[0]
[7]
[0]
[8]
[0]
[9]
[1]
[0]
[1]
[1]
[1]
[2]
[1]
[3]
[1]
[4]
[1]
[5]
R140
ct_y_mode
[1]
[6]
[1]
[7]
[1]
[8]
[1]
[9]
[2]
[0]
[2]
[1]
[2]
[2]
[2]
[3]
[2]
[4]
[2]
[5]
[2]
[6]
[2]
[7]
[2]
[8]
[2]
[9]
[3]
[0]
[3]
[1]
R141
ct_y_mode
ct_partition
[3]
[2]
[3]
[3]
[3]
[4]
[3]
[5]
[3]
[6]
[3]
[7]
[3]
[8]
[3]
[9]
[0]
[0]
[0]
[1]
[0]
[2]
[0]
[3]
[1]
[0]
[1]
[1]
[1]
[2]
[1]
[3]
R142
ct_partition
[2]
[0]
[2]
[1]
[2]
[2]
[2]
[3]
[3]
[0]
[3]
[1]
[3]
[2]
[3]
[3]
[4]
[0]
[4]
[1]
[4]
[2]
[4]
[3]
[5]
[0]
[5]
[1]
[5]
[2]
[5]
[3]
R143
ct_partition
[6]
[0]
[6]
[1]
[6]
[2]
[6]
[3]
[7]
[0]
[7]
[1]
[7]
[2]
[7]
[3]
[8]
[0]
[8]
[1]
[8]
[2]
[8]
[3]
[9]
[0]
[9]
[1]
[9]
[2]
[9]
[3]
R144
ct_partition
[10]
[0]
[10]
[1]
[10]
[2]
[10]
[3]
[11]
[0]
[11]
[1]
[11]
[2]
[11]
[3]
[12]
[0]
[12]
[1]
[12]
[2]
[12]
[3]
[13]
[0]
[13]
[1]
[13]
[2]
[13]
[3]
R145
ct_partition
ct_mv_joints
ct_mv_sign
ct_mv_classes
HEVC
44
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[14]
[0]
[14]
[1]
[14]
[2]
[14]
[3]
[15]
[0]
[15]
[1]
[15]
[2]
[15]
[3]
[0]
[1]
[2]
[3]
[0]
[0]
[0]
[1]
[0]
[0]
[0]
[1]
R146
ct_mv_classes
ct_mv_class0
ct_mv_bits
[0]
[2]
[0]
[3]
[0]
[4]
[0]
[5]
[0]
[6]
[0]
[7]
[0]
[8]
[0]
[9]
[0]
[10]
[0]
[0]
[0]
[1]
[0]
[0]
[0]
[0]
[0]
[1]
[0]
[1]
[0]
[0]
[1]
[1]
[0]
[2]
[0]
R147
ct_mv_bits
ct_mv_sign
[0]
[2]
[1]
[0]
[3]
[0]
[0]
[3]
[1]
[0]
[4]
[0]
[0]
[4]
[1]
[0]
[5]
[0]
[0]
[5]
[1]
[0]
[6]
[0]
[0]
[6]
[1]
[0]
[7]
[0]
[0]
[7]
[1]
[0]
[8]
[0]
[0]
[8]
[1]
[0]
[9]
[0]
[0]
[9]
[1]
[1]
[0]
R148
ct_mv_sign
ct_mv_classes
ct_mv_class0
ct_mv_bits
[1]
[1]
[1]
[0]
[1]
[1]
[1]
[2]
[1]
[3]
[1]
[4]
[1]
[5]
[1]
[6]
[1]
[7]
[1]
[8]
[1]
[9]
[1]
[10]
[1]
[0]
[1]
[1]
[1]
[0]
[0]
[1]
[0]
[1]
R149
ct_mv_bits
[1]
[1]
[0]
[1]
[1]
[1]
[1]
[2]
[0]
[1]
[2]
[1]
[1]
[3]
[0]
[1]
[3]
[1]
[1]
[4]
[0]
[1]
[4]
[1]
[1]
[5]
[0]
[1]
[5]
[1]
[1]
[6]
[0]
[1]
[6]
[1]
[1]
[7]
[0]
[1]
[7]
[1]
[1]
[8]
[0]
[1]
[8]
[1]
R150
ct_mv_bits
ct_mv_class0_fp
ct_mv_fp
ct_mv_class0_fp
[1]
[9]
[0]
[1]
[9]
[1]
[0]
[0]
[0]
[0]
[0]
[1]
[0]
[0]
[2]
[0]
[0]
[3]
[0]
[1]
[0]
[0]
[1]
[1]
[0]
[1]
[2]
[0]
[1]
[3]
[0]
[0]
[0]
[1]
[0]
[2]
[0]
[3]
[1]
[0]
[0]
[1]
[0]
[1]
R151
ct_mv_class0_fp
ct_mv_fp
ct_mv_class0_hp
ct_mv_hp
ct_mv_class0_hp
[1]
[0]
[2]
[1]
[0]
[3]
[1]
[1]
[0]
[1]
[1]
[1]
[1]
[1]
[2]
[1]
[1]
[3]
[1]
[0]
[1]
[1]
[1]
[2]
[1]
[3]
[0]
[0]
[0]
[1]
[0]
[0]
[0]
[1]
[1]
[0]
[1]
[1]
R152
ct_mv_hp
ct_eob_br
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
45
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[1]
[0]
[1]
[1]
[T=0]
[B=0]
[R=0]
[CB=0]
[CT=0]
[T=0]
[B=0]
[R=0]
[CB=0]
[CT=1]
[T=0]
[B=0]
[R=0]
[CB=0]
[CT=2]
[T=0]
[B=0]
[R=0]
[CB=1]
[CT=0]
[T=0]
[B=0]
[R=0]
[CB=1]
[CT=1]
[T=0]
[B=0]
[R=0]
[CB=1]
[CT=2]
[T=0]
[B=0]
[R=0]
[CB=1]
[CT=3]
[T=0]
[B=0]
[R=0]
[CB=1]
[CT=4]
[T=0]
[B=0]
[R=0]
[CB=1]
[CT=5]
[T=0]
[B=0]
[R=0]
[CB=2]
[CT=0]
[T=0]
[B=0]
[R=0]
[CB=2]
[CT=1]
[T=0]
[B=0]
[R=0]
[CB=2]
[CT=2]
[T=0]
[B=0]
[R=0]
[CB=2]
[CT=3]
[T=0]
[B=0]
[R=0]
[CB=2]
[CT=4]
R153
ct_eob_br
[T=0]
[B=0]
[R=0]
[CB=2]
[CT=5]
[T=0]
[B=0]
[R=0]
[CB=3]
[CT=0]
[T=0]
[B=0]
[R=0]
[CB=3]
[CT=1]
[T=0]
[B=0]
[R=0]
[CB=3]
[CT=2]
[T=0]
[B=0]
[R=0]
[CB=3]
[CT=3]
[T=0]
[B=0]
[R=0]
[CB=3]
[CT=4]
[T=0]
[B=0]
[R=0]
[CB=3]
[CT=5]
[T=0]
[B=0]
[R=0]
[CB=4]
[CT=0]
[T=0]
[B=0]
[R=0]
[CB=4]
[CT=1]
[T=0]
[B=0]
[R=0]
[CB=4]
[CT=2]
[T=0]
[B=0]
[R=0]
[CB=4]
[CT=3]
[T=0]
[B=0]
[R=0]
[CB=4]
[CT=4]
[T=0]
[B=0]
[R=0]
[CB=4]
[CT=5]
[T=0]
[B=0]
[R=0]
[CB=5]
[CT=0]
[T=0]
[B=0]
[R=0]
[CB=5]
[CT=1]
[T=0]
[B=0]
[R=0]
[CB=5]
[CT=2]
R154
ct_eob_br
[T=0]
[B=0]
[R=0]
[CB=5]
[CT=3]
[T=0]
[B=0]
[R=0]
[CB=5]
[CT=4]
[T=0]
[B=0]
[R=0]
[CB=5]
[CT=5]
[T=0]
[B=0]
[R=1]
[CB=0]
[CT=0]
[T=0]
[B=0]
[R=1]
[CB=0]
[CT=1]
[T=0]
[B=0]
[R=1]
[CB=0]
[CT=2]
[T=0]
[B=0]
[R=1]
[CB=1]
[CT=0]
[T=0]
[B=0]
[R=1]
[CB=1]
[CT=1]
[T=0]
[B=0]
[R=1]
[CB=1]
[CT=2]
[T=0]
[B=0]
[R=1]
[CB=1]
[CT=3]
[T=0]
[B=0]
[R=1]
[CB=1]
[CT=4]
[T=0]
[B=0]
[R=1]
[CB=1]
[CT=5]
[T=0]
[B=0]
[R=1]
[CB=2]
[CT=0]
[T=0]
[B=0]
[R=1]
[CB=2]
[CT=1]
[T=0]
[B=0]
[R=1]
[CB=2]
[CT=2]
[T=0]
[B=0]
[R=1]
[CB=2]
[CT=3]
R155
ct_eob_br
[T=0]
[B=0]
[R=1]
[CB=2]
[CT=4]
[T=0]
[B=0]
[R=1]
[CB=2]
[T=0]
[B=0]
[R=1]
[CB=3]
[T=0]
[B=0]
[R=1]
[CB=3]
[T=0]
[B=0]
[R=1]
[CB=3]
[T=0]
[B=0]
[R=1]
[CB=3]
[T=0]
[B=0]
[R=1]
[CB=3]
[T=0]
[B=0]
[R=1]
[CB=3]
[T=0]
[B=0]
[R=1]
[CB=4]
[T=0]
[B=0]
[R=1]
[CB=4]
[T=0]
[B=0]
[R=1]
[CB=4]
[T=0]
[B=0]
[R=1]
[CB=4]
[T=0]
[B=0]
[R=1]
[CB=4]
[T=0]
[B=0]
[R=1]
[CB=4]
[T=0]
[B=0]
[R=1]
[CB=5]
[T=0]
[B=0]
[R=1]
[CB=5]
[CT=1]
HEVC
46
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[CT=5]
[CT=0]
[CT=1]
[CT=2]
[CT=3]
[CT=4]
[CT=5]
[CT=0]
[CT=1]
[CT=2]
[CT=3]
[CT=4]
[CT=5]
[CT=0]
R156
ct_eob_br
[T=0]
[B=0]
[R=1]
[CB=5]
[CT=2]
[T=0]
[B=0]
[R=1]
[CB=5]
[CT=3]
[T=0]
[B=0]
[R=1]
[CB=5]
[CT=4]
[T=0]
[B=0]
[R=1]
[CB=5]
[CT=5]
[T=0]
[B=1]
[R=0]
[CB=0]
[CT=0]
[T=0]
[B=1]
[R=0]
[CB=0]
[CT=1]
[T=0]
[B=1]
[R=0]
[CB=0]
[CT=2]
[T=0]
[B=1]
[R=0]
[CB=1]
[CT=0]
[T=0]
[B=1]
[R=0]
[CB=1]
[CT=1]
[T=0]
[B=1]
[R=0]
[CB=1]
[CT=2]
[T=0]
[B=1]
[R=0]
[CB=1]
[CT=3]
[T=0]
[B=1]
[R=0]
[CB=1]
[CT=4]
[T=0]
[B=1]
[R=0]
[CB=1]
[CT=5]
[T=0]
[B=1]
[R=0]
[CB=2]
[CT=0]
[T=0]
[B=1]
[R=0]
[CB=2]
[CT=1]
[T=0]
[B=1]
[R=0]
[CB=2]
[CT=2]
R157
ct_eob_br
[T=0]
[B=1]
[R=0]
[CB=2]
[CT=3]
[T=0]
[B=1]
[R=0]
[CB=2]
[CT=4]
[T=0]
[B=1]
[R=0]
[CB=2]
[CT=5]
[T=0]
[B=1]
[R=0]
[CB=3]
[CT=0]
[T=0]
[B=1]
[R=0]
[CB=3]
[CT=1]
[T=0]
[B=1]
[R=0]
[CB=3]
[CT=2]
[T=0]
[B=1]
[R=0]
[CB=3]
[CT=3]
[T=0]
[B=1]
[R=0]
[CB=3]
[CT=4]
[T=0]
[B=1]
[R=0]
[CB=3]
[CT=5]
[T=0]
[B=1]
[R=0]
[CB=4]
[CT=0]
[T=0]
[B=1]
[R=0]
[CB=4]
[CT=1]
[T=0]
[B=1]
[R=0]
[CB=4]
[CT=2]
[T=0]
[B=1]
[R=0]
[CB=4]
[CT=3]
[T=0]
[B=1]
[R=0]
[CB=4]
[CT=4]
[T=0]
[B=1]
[R=0]
[CB=4]
[CT=5]
[T=0]
[B=1]
[R=0]
[CB=5]
[CT=0]
R158
ct_eob_br
[T=0]
[B=1]
[R=0]
[CB=5]
[CT=1]
[T=0]
[B=1]
[R=0]
[CB=5]
[CT=2]
[T=0]
[B=1]
[R=0]
[CB=5]
[CT=3]
[T=0]
[B=1]
[R=0]
[CB=5]
[CT=4]
[T=0]
[B=1]
[R=0]
[CB=5]
[CT=5]
[T=0]
[B=1]
[R=1]
[CB=0]
[CT=0]
[T=0]
[B=1]
[R=1]
[CB=0]
[CT=1]
[T=0]
[B=1]
[R=1]
[CB=0]
[CT=2]
[T=0]
[B=1]
[R=1]
[CB=1]
[CT=0]
[T=0]
[B=1]
[R=1]
[CB=1]
[CT=1]
[T=0]
[B=1]
[R=1]
[CB=1]
[CT=2]
[T=0]
[B=1]
[R=1]
[CB=1]
[CT=3]
[T=0]
[B=1]
[R=1]
[CB=1]
[CT=4]
[T=0]
[B=1]
[R=1]
[CB=1]
[CT=5]
[T=0]
[B=1]
[R=1]
[CB=2]
[CT=0]
[T=0]
[B=1]
[R=1]
[CB=2]
[CT=1]
R159
ct_eob_br
[T=0]
[B=1]
[T=0]
[B=1]
[T=0]
[B=1]
[T=0]
[B=1]
[T=0]
[B=1]
[T=0]
[B=1]
[T=0]
[B=1]
[T=0]
[B=1]
[T=0]
[B=1]
[T=0]
[B=1]
[T=0]
[B=1]
[T=0]
[B=1]
[T=0]
[B=1]
[T=0]
[B=1]
[T=0]
[B=1]
[T=0]
[B=1]
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
47
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[R=1]
[CB=2]
[CT=2]
[R=1]
[CB=2]
[CT=3]
[R=1]
[CB=2]
[CT=4]
[R=1]
[CB=2]
[CT=5]
[R=1]
[CB=3]
[CT=0]
[R=1]
[CB=3]
[CT=1]
[R=1]
[CB=3]
[CT=2]
[R=1]
[CB=3]
[CT=3]
[R=1]
[CB=3]
[CT=4]
[R=1]
[CB=3]
[CT=5]
[R=1]
[CB=4]
[CT=0]
[R=1]
[CB=4]
[CT=1]
[R=1]
[CB=4]
[CT=2]
[R=1]
[CB=4]
[CT=3]
[R=1]
[CB=4]
[CT=4]
[R=1]
[CB=4]
[CT=5]
R160
ct_eob_br
[T=0]
[B=1]
[R=1]
[CB=5]
[CT=0]
[T=0]
[B=1]
[R=1]
[CB=5]
[CT=1]
[T=0]
[B=1]
[R=1]
[CB=5]
[CT=2]
[T=0]
[B=1]
[R=1]
[CB=5]
[CT=3]
[T=0]
[B=1]
[R=1]
[CB=5]
[CT=4]
[T=0]
[B=1]
[R=1]
[CB=5]
[CT=5]
[T=1]
[B=0]
[R=0]
[CB=0]
[CT=0]
[T=1]
[B=0]
[R=0]
[CB=0]
[CT=1]
[T=1]
[B=0]
[R=0]
[CB=0]
[CT=2]
[T=1]
[B=0]
[R=0]
[CB=1]
[CT=0]
[T=1]
[B=0]
[R=0]
[CB=1]
[CT=1]
[T=1]
[B=0]
[R=0]
[CB=1]
[CT=2]
[T=1]
[B=0]
[R=0]
[CB=1]
[CT=3]
[T=1]
[B=0]
[R=0]
[CB=1]
[CT=4]
[T=1]
[B=0]
[R=0]
[CB=1]
[CT=5]
[T=1]
[B=0]
[R=0]
[CB=2]
[CT=0]
R161
ct_eob_br
[T=1]
[B=0]
[R=0]
[CB=2]
[CT=1]
[T=1]
[B=0]
[R=0]
[CB=2]
[CT=2]
[T=1]
[B=0]
[R=0]
[CB=2]
[CT=3]
[T=1]
[B=0]
[R=0]
[CB=2]
[CT=4]
[T=1]
[B=0]
[R=0]
[CB=2]
[CT=5]
[T=1]
[B=0]
[R=0]
[CB=3]
[CT=0]
[T=1]
[B=0]
[R=0]
[CB=3]
[CT=1]
[T=1]
[B=0]
[R=0]
[CB=3]
[CT=2]
[T=1]
[B=0]
[R=0]
[CB=3]
[CT=3]
[T=1]
[B=0]
[R=0]
[CB=3]
[CT=4]
[T=1]
[B=0]
[R=0]
[CB=3]
[CT=5]
[T=1]
[B=0]
[R=0]
[CB=4]
[CT=0]
[T=1]
[B=0]
[R=0]
[CB=4]
[CT=1]
[T=1]
[B=0]
[R=0]
[CB=4]
[CT=2]
[T=1]
[B=0]
[R=0]
[CB=4]
[CT=3]
[T=1]
[B=0]
[R=0]
[CB=4]
[CT=4]
R162
ct_eob_br
[T=1]
[B=0]
[R=0]
[CB=4]
[CT=5]
[T=1]
[B=0]
[R=0]
[CB=5]
[CT=0]
[T=1]
[B=0]
[R=0]
[CB=5]
[CT=1]
[T=1]
[B=0]
[R=0]
[CB=5]
[CT=2]
[T=1]
[B=0]
[R=0]
[CB=5]
[CT=3]
[T=1]
[B=0]
[R=0]
[CB=5]
[CT=4]
[T=1]
[B=0]
[R=0]
[CB=5]
[CT=5]
[T=1]
[B=0]
[R=1]
[CB=0]
[CT=0]
[T=1]
[B=0]
[R=1]
[CB=0]
[CT=1]
[T=1]
[B=0]
[R=1]
[CB=0]
[CT=2]
[T=1]
[B=0]
[R=1]
[CB=1]
[CT=0]
[T=1]
[B=0]
[R=1]
[CB=1]
[CT=1]
[T=1]
[B=0]
[R=1]
[CB=1]
[CT=2]
[T=1]
[B=0]
[R=1]
[CB=1]
[CT=3]
[T=1]
[B=0]
[R=1]
[CB=1]
[CT=4]
[T=1]
[B=0]
[R=1]
[CB=1]
[CT=5]
HEVC
48
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R163
ct_eob_br
[T=1]
[B=0]
[R=1]
[CB=2]
[CT=0]
[T=1]
[B=0]
[R=1]
[CB=2]
[CT=1]
[T=1]
[B=0]
[R=1]
[CB=2]
[CT=2]
[T=1]
[B=0]
[R=1]
[CB=2]
[CT=3]
[T=1]
[B=0]
[R=1]
[CB=2]
[CT=4]
[T=1]
[B=0]
[R=1]
[CB=2]
[CT=5]
[T=1]
[B=0]
[R=1]
[CB=3]
[CT=0]
[T=1]
[B=0]
[R=1]
[CB=3]
[CT=1]
[T=1]
[B=0]
[R=1]
[CB=3]
[CT=2]
[T=1]
[B=0]
[R=1]
[CB=3]
[CT=3]
[T=1]
[B=0]
[R=1]
[CB=3]
[CT=4]
[T=1]
[B=0]
[R=1]
[CB=3]
[CT=5]
[T=1]
[B=0]
[R=1]
[CB=4]
[CT=0]
[T=1]
[B=0]
[R=1]
[CB=4]
[CT=1]
[T=1]
[B=0]
[R=1]
[CB=4]
[CT=2]
[T=1]
[B=0]
[R=1]
[CB=4]
[CT=3]
R164
ct_eob_br
[T=1]
[B=0]
[R=1]
[CB=4]
[CT=4]
[T=1]
[B=0]
[R=1]
[CB=4]
[CT=5]
[T=1]
[B=0]
[R=1]
[CB=5]
[CT=0]
[T=1]
[B=0]
[R=1]
[CB=5]
[CT=1]
[T=1]
[B=0]
[R=1]
[CB=5]
[CT=2]
[T=1]
[B=0]
[R=1]
[CB=5]
[CT=3]
[T=1]
[B=0]
[R=1]
[CB=5]
[CT=4]
[T=1]
[B=0]
[R=1]
[CB=5]
[CT=5]
[T=1]
[B=1]
[R=0]
[CB=0]
[CT=0]
[T=1]
[B=1]
[R=0]
[CB=0]
[CT=1]
[T=1]
[B=1]
[R=0]
[CB=0]
[CT=2]
[T=1]
[B=1]
[R=0]
[CB=1]
[CT=0]
[T=1]
[B=1]
[R=0]
[CB=1]
[CT=1]
[T=1]
[B=1]
[R=0]
[CB=1]
[CT=2]
[T=1]
[B=1]
[R=0]
[CB=1]
[CT=3]
[T=1]
[B=1]
[R=0]
[CB=1]
[CT=4]
R165
ct_eob_br
[T=1]
[B=1]
[R=0]
[CB=1]
[CT=5]
[T=1]
[B=1]
[R=0]
[CB=2]
[CT=0]
[T=1]
[B=1]
[R=0]
[CB=2]
[CT=1]
[T=1]
[B=1]
[R=0]
[CB=2]
[CT=2]
[T=1]
[B=1]
[R=0]
[CB=2]
[CT=3]
[T=1]
[B=1]
[R=0]
[CB=2]
[CT=4]
[T=1]
[B=1]
[R=0]
[CB=2]
[CT=5]
[T=1]
[B=1]
[R=0]
[CB=3]
[CT=0]
[T=1]
[B=1]
[R=0]
[CB=3]
[CT=1]
[T=1]
[B=1]
[R=0]
[CB=3]
[CT=2]
[T=1]
[B=1]
[R=0]
[CB=3]
[CT=3]
[T=1]
[B=1]
[R=0]
[CB=3]
[CT=4]
[T=1]
[B=1]
[R=0]
[CB=3]
[CT=5]
[T=1]
[B=1]
[R=0]
[CB=4]
[CT=0]
[T=1]
[B=1]
[R=0]
[CB=4]
[CT=1]
[T=1]
[B=1]
[R=0]
[CB=4]
[CT=2]
R166
ct_eob_br
[T=1]
[B=1]
[R=0]
[CB=4]
[T=1]
[B=1]
[R=0]
[T=1]
[B=1]
[R=0]
[T=1]
[B=1]
[R=0]
[T=1]
[B=1]
[R=0]
[T=1]
[B=1]
[R=0]
[T=1]
[B=1]
[R=0]
[T=1]
[B=1]
[R=0]
[T=1]
[B=1]
[R=0]
[T=1]
[B=1]
[R=1]
[T=1]
[B=1]
[R=1]
[T=1]
[B=1]
[R=1]
[T=1]
[B=1]
[R=1]
[T=1]
[B=1]
[R=1]
[T=1]
[B=1]
[R=1]
[T=1]
[B=1]
[R=1]
[CB=1]
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
49
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[CT=3]
[CB=4]
[CT=4]
[CB=4]
[CT=5]
[CB=5]
[CT=0]
[CB=5]
[CT=1]
[CB=5]
[CT=2]
[CB=5]
[CT=3]
[CB=5]
[CT=4]
[CB=5]
[CT=5]
[CB=0]
[CT=0]
[CB=0]
[CT=1]
[CB=0]
[CT=2]
[CB=1]
[CT=0]
[CB=1]
[CT=1]
[CB=1]
[CT=2]
[CT=3]
R167
ct_eob_br
[T=1]
[B=1]
[R=1]
[CB=1]
[CT=4]
[T=1]
[B=1]
[R=1]
[CB=1]
[CT=5]
[T=1]
[B=1]
[R=1]
[CB=2]
[CT=0]
[T=1]
[B=1]
[R=1]
[CB=2]
[CT=1]
[T=1]
[B=1]
[R=1]
[CB=2]
[CT=2]
[T=1]
[B=1]
[R=1]
[CB=2]
[CT=3]
[T=1]
[B=1]
[R=1]
[CB=2]
[CT=4]
[T=1]
[B=1]
[R=1]
[CB=2]
[CT=5]
[T=1]
[B=1]
[R=1]
[CB=3]
[CT=0]
[T=1]
[B=1]
[R=1]
[CB=3]
[CT=1]
[T=1]
[B=1]
[R=1]
[CB=3]
[CT=2]
[T=1]
[B=1]
[R=1]
[CB=3]
[CT=3]
[T=1]
[B=1]
[R=1]
[CB=3]
[CT=4]
[T=1]
[B=1]
[R=1]
[CB=3]
[CT=5]
[T=1]
[B=1]
[R=1]
[CB=4]
[CT=0]
[T=1]
[B=1]
[R=1]
[CB=4]
[CT=1]
R168
ct_eob_br
[T=1]
[B=1]
[R=1]
[CB=4]
[CT=2]
[T=1]
[B=1]
[R=1]
[CB=4]
[CT=3]
[T=1]
[B=1]
[R=1]
[CB=4]
[CT=4]
[T=1]
[B=1]
[R=1]
[CB=4]
[CT=5]
[T=1]
[B=1]
[R=1]
[CB=5]
[CT=0]
[T=1]
[B=1]
[R=1]
[CB=5]
[CT=1]
[T=1]
[B=1]
[R=1]
[CB=5]
[CT=2]
[T=1]
[B=1]
[R=1]
[CB=5]
[CT=3]
[T=1]
[B=1]
[R=1]
[CB=5]
[CT=4]
[T=1]
[B=1]
[R=1]
[CB=5]
[CT=5]
[T=2]
[B=0]
[R=0]
[CB=0]
[CT=0]
[T=2]
[B=0]
[R=0]
[CB=0]
[CT=1]
[T=2]
[B=0]
[R=0]
[CB=0]
[CT=2]
[T=2]
[B=0]
[R=0]
[CB=1]
[CT=0]
[T=2]
[B=0]
[R=0]
[CB=1]
[CT=1]
[T=2]
[B=0]
[R=0]
[CB=1]
[CT=2]
R169
ct_eob_br
[T=2]
[B=0]
[R=0]
[CB=1]
[CT=3]
[T=2]
[B=0]
[R=0]
[CB=1]
[CT=4]
[T=2]
[B=0]
[R=0]
[CB=1]
[CT=5]
[T=2]
[B=0]
[R=0]
[CB=2]
[CT=0]
[T=2]
[B=0]
[R=0]
[CB=2]
[CT=1]
[T=2]
[B=0]
[R=0]
[CB=2]
[CT=2]
[T=2]
[B=0]
[R=0]
[CB=2]
[CT=3]
[T=2]
[B=0]
[R=0]
[CB=2]
[CT=4]
[T=2]
[B=0]
[R=0]
[CB=2]
[CT=5]
[T=2]
[B=0]
[R=0]
[CB=3]
[CT=0]
[T=2]
[B=0]
[R=0]
[CB=3]
[CT=1]
[T=2]
[B=0]
[R=0]
[CB=3]
[CT=2]
[T=2]
[B=0]
[R=0]
[CB=3]
[CT=3]
[T=2]
[B=0]
[R=0]
[CB=3]
[CT=4]
[T=2]
[B=0]
[R=0]
[CB=3]
[CT=5]
[T=2]
[B=0]
[R=0]
[CB=4]
[CT=0]
R170
ct_eob_br
[T=2]
[T=2]
[T=2]
[T=2]
[T=2]
[T=2]
[T=2]
[T=2]
[T=2]
[T=2]
[T=2]
[T=2]
[T=2]
[T=2]
[T=2]
[T=2]
HEVC
50
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[B=0]
[R=0]
[CB=4]
[CT=1]
[B=0]
[R=0]
[CB=4]
[CT=2]
[B=0]
[R=0]
[CB=4]
[CT=3]
[B=0]
[R=0]
[CB=4]
[CT=4]
[B=0]
[R=0]
[CB=4]
[CT=5]
[B=0]
[R=0]
[CB=5]
[CT=0]
[B=0]
[R=0]
[CB=5]
[CT=1]
[B=0]
[R=0]
[CB=5]
[CT=2]
[B=0]
[R=0]
[CB=5]
[CT=3]
[B=0]
[R=0]
[CB=5]
[CT=4]
[B=0]
[R=0]
[CB=5]
[CT=5]
[B=0]
[R=1]
[CB=0]
[CT=0]
[B=0]
[R=1]
[CB=0]
[CT=1]
[B=0]
[R=1]
[CB=0]
[CT=2]
[B=0]
[R=1]
[CB=1]
[CT=0]
[B=0]
[R=1]
[CB=1]
[CT=1]
R171
ct_eob_br
[T=2]
[B=0]
[R=1]
[CB=1]
[CT=2]
[T=2]
[B=0]
[R=1]
[CB=1]
[CT=3]
[T=2]
[B=0]
[R=1]
[CB=1]
[CT=4]
[T=2]
[B=0]
[R=1]
[CB=1]
[CT=5]
[T=2]
[B=0]
[R=1]
[CB=2]
[CT=0]
[T=2]
[B=0]
[R=1]
[CB=2]
[CT=1]
[T=2]
[B=0]
[R=1]
[CB=2]
[CT=2]
[T=2]
[B=0]
[R=1]
[CB=2]
[CT=3]
[T=2]
[B=0]
[R=1]
[CB=2]
[CT=4]
[T=2]
[B=0]
[R=1]
[CB=2]
[CT=5]
[T=2]
[B=0]
[R=1]
[CB=3]
[CT=0]
[T=2]
[B=0]
[R=1]
[CB=3]
[CT=1]
[T=2]
[B=0]
[R=1]
[CB=3]
[CT=2]
[T=2]
[B=0]
[R=1]
[CB=3]
[CT=3]
[T=2]
[B=0]
[R=1]
[CB=3]
[CT=4]
[T=2]
[B=0]
[R=1]
[CB=3]
[CT=5]
R172
ct_eob_br
[T=2]
[B=0]
[R=1]
[CB=4]
[CT=0]
[T=2]
[B=0]
[R=1]
[CB=4]
[CT=1]
[T=2]
[B=0]
[R=1]
[CB=4]
[CT=2]
[T=2]
[B=0]
[R=1]
[CB=4]
[CT=3]
[T=2]
[B=0]
[R=1]
[CB=4]
[CT=4]
[T=2]
[B=0]
[R=1]
[CB=4]
[CT=5]
[T=2]
[B=0]
[R=1]
[CB=5]
[CT=0]
[T=2]
[B=0]
[R=1]
[CB=5]
[CT=1]
[T=2]
[B=0]
[R=1]
[CB=5]
[CT=2]
[T=2]
[B=0]
[R=1]
[CB=5]
[CT=3]
[T=2]
[B=0]
[R=1]
[CB=5]
[CT=4]
[T=2]
[B=0]
[R=1]
[CB=5]
[CT=5]
[T=2]
[B=1]
[R=0]
[CB=0]
[CT=0]
[T=2]
[B=1]
[R=0]
[CB=0]
[CT=1]
[T=2]
[B=1]
[R=0]
[CB=0]
[CT=2]
[T=2]
[B=1]
[R=0]
[CB=1]
[CT=0]
R173
ct_eob_br
[T=2]
[B=1]
[R=0]
[CB=1]
[CT=1]
[T=2]
[B=1]
[R=0]
[CB=1]
[T=2]
[B=1]
[R=0]
[CB=1]
[T=2]
[B=1]
[R=0]
[CB=1]
[T=2]
[B=1]
[R=0]
[CB=1]
[T=2]
[B=1]
[R=0]
[CB=2]
[T=2]
[B=1]
[R=0]
[CB=2]
[T=2]
[B=1]
[R=0]
[CB=2]
[T=2]
[B=1]
[R=0]
[CB=2]
[T=2]
[B=1]
[R=0]
[CB=2]
[T=2]
[B=1]
[R=0]
[CB=2]
[CT=5]
[T=2]
[B=1]
[R=0]
[CB=3]
[CT=0]
[T=2]
[B=1]
[R=0]
[CB=3]
[T=2]
[B=1]
[R=0]
[CB=3]
[T=2]
[B=1]
[R=0]
[CB=3]
[T=2]
[B=1]
[R=0]
[CB=3]
[CT=4]
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
51
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[CT=2]
[CT=3]
[CT=4]
[CT=5]
[CT=0]
[CT=1]
[CT=2]
[CT=3]
[CT=4]
[CT=1]
[CT=2]
[CT=3]
R174
ct_eob_br
[T=2]
[B=1]
[R=0]
[CB=3]
[CT=5]
[T=2]
[B=1]
[R=0]
[CB=4]
[CT=0]
[T=2]
[B=1]
[R=0]
[CB=4]
[CT=1]
[T=2]
[B=1]
[R=0]
[CB=4]
[CT=2]
[T=2]
[B=1]
[R=0]
[CB=4]
[CT=3]
[T=2]
[B=1]
[R=0]
[CB=4]
[CT=4]
[T=2]
[B=1]
[R=0]
[CB=4]
[CT=5]
[T=2]
[B=1]
[R=0]
[CB=5]
[CT=0]
[T=2]
[B=1]
[R=0]
[CB=5]
[CT=1]
[T=2]
[B=1]
[R=0]
[CB=5]
[CT=2]
[T=2]
[B=1]
[R=0]
[CB=5]
[CT=3]
[T=2]
[B=1]
[R=0]
[CB=5]
[CT=4]
[T=2]
[B=1]
[R=0]
[CB=5]
[CT=5]
[T=2]
[B=1]
[R=1]
[CB=0]
[CT=0]
[T=2]
[B=1]
[R=1]
[CB=0]
[CT=1]
[T=2]
[B=1]
[R=1]
[CB=0]
[CT=2]
R175
ct_eob_br
[T=2]
[B=1]
[R=1]
[CB=1]
[CT=0]
[T=2]
[B=1]
[R=1]
[CB=1]
[CT=1]
[T=2]
[B=1]
[R=1]
[CB=1]
[CT=2]
[T=2]
[B=1]
[R=1]
[CB=1]
[CT=3]
[T=2]
[B=1]
[R=1]
[CB=1]
[CT=4]
[T=2]
[B=1]
[R=1]
[CB=1]
[CT=5]
[T=2]
[B=1]
[R=1]
[CB=2]
[CT=0]
[T=2]
[B=1]
[R=1]
[CB=2]
[CT=1]
[T=2]
[B=1]
[R=1]
[CB=2]
[CT=2]
[T=2]
[B=1]
[R=1]
[CB=2]
[CT=3]
[T=2]
[B=1]
[R=1]
[CB=2]
[CT=4]
[T=2]
[B=1]
[R=1]
[CB=2]
[CT=5]
[T=2]
[B=1]
[R=1]
[CB=3]
[CT=0]
[T=2]
[B=1]
[R=1]
[CB=3]
[CT=1]
[T=2]
[B=1]
[R=1]
[CB=3]
[CT=2]
[T=2]
[B=1]
[R=1]
[CB=3]
[CT=3]
R176
ct_eob_br
[T=2]
[B=1]
[R=1]
[CB=3]
[CT=4]
[T=2]
[B=1]
[R=1]
[CB=3]
[CT=5]
[T=2]
[B=1]
[R=1]
[CB=4]
[CT=0]
[T=2]
[B=1]
[R=1]
[CB=4]
[CT=1]
[T=2]
[B=1]
[R=1]
[CB=4]
[CT=2]
[T=2]
[B=1]
[R=1]
[CB=4]
[CT=3]
[T=2]
[B=1]
[R=1]
[CB=4]
[CT=4]
[T=2]
[B=1]
[R=1]
[CB=4]
[CT=5]
[T=2]
[B=1]
[R=1]
[CB=5]
[CT=0]
[T=2]
[B=1]
[R=1]
[CB=5]
[CT=1]
[T=2]
[B=1]
[R=1]
[CB=5]
[CT=2]
[T=2]
[B=1]
[R=1]
[CB=5]
[CT=3]
[T=2]
[B=1]
[R=1]
[CB=5]
[CT=4]
[T=2]
[B=1]
[R=1]
[CB=5]
[CT=5]
[T=3]
[B=0]
[R=0]
[CB=0]
[CT=0]
[T=3]
[B=0]
[R=0]
[CB=0]
[CT=1]
R177
ct_eob_br
[T=3]
[B=0]
[R=0]
[T=3]
[B=0]
[R=0]
[T=3]
[B=0]
[R=0]
[T=3]
[B=0]
[R=0]
[T=3]
[B=0]
[R=0]
[T=3]
[B=0]
[R=0]
[T=3]
[B=0]
[R=0]
[T=3]
[B=0]
[R=0]
[T=3]
[B=0]
[R=0]
[T=3]
[B=0]
[R=0]
[T=3]
[B=0]
[R=0]
[T=3]
[B=0]
[R=0]
[T=3]
[B=0]
[R=0]
[T=3]
[B=0]
[R=0]
[T=3]
[B=0]
[R=0]
[T=3]
[B=0]
[R=0]
HEVC
52
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[CB=0]
[CT=2]
[CB=1]
[CT=0]
[CB=1]
[CT=1]
[CB=1]
[CT=2]
[CB=1]
[CT=3]
[CB=1]
[CT=4]
[CB=1]
[CT=5]
[CB=2]
[CT=0]
[CB=2]
[CT=1]
[CB=2]
[CT=2]
[CB=2]
[CT=3]
[CB=2]
[CT=4]
[CB=2]
[CT=5]
[CB=3]
[CT=0]
[CB=3]
[CT=1]
[CB=3]
[CT=2]
R178
ct_eob_br
[T=3]
[B=0]
[R=0]
[CB=3]
[CT=3]
[T=3]
[B=0]
[R=0]
[CB=3]
[CT=4]
[T=3]
[B=0]
[R=0]
[CB=3]
[CT=5]
[T=3]
[B=0]
[R=0]
[CB=4]
[CT=0]
[T=3]
[B=0]
[R=0]
[CB=4]
[CT=1]
[T=3]
[B=0]
[R=0]
[CB=4]
[CT=2]
[T=3]
[B=0]
[R=0]
[CB=4]
[CT=3]
[T=3]
[B=0]
[R=0]
[CB=4]
[CT=4]
[T=3]
[B=0]
[R=0]
[CB=4]
[CT=5]
[T=3]
[B=0]
[R=0]
[CB=5]
[CT=0]
[T=3]
[B=0]
[R=0]
[CB=5]
[CT=1]
[T=3]
[B=0]
[R=0]
[CB=5]
[CT=2]
[T=3]
[B=0]
[R=0]
[CB=5]
[CT=3]
[T=3]
[B=0]
[R=0]
[CB=5]
[CT=4]
[T=3]
[B=0]
[R=0]
[CB=5]
[CT=5]
[T=3]
[B=0]
[R=1]
[CB=0]
[CT=0]
R179
ct_eob_br
[T=3]
[B=0]
[R=1]
[CB=0]
[CT=1]
[T=3]
[B=0]
[R=1]
[CB=0]
[CT=2]
[T=3]
[B=0]
[R=1]
[CB=1]
[CT=0]
[T=3]
[B=0]
[R=1]
[CB=1]
[CT=1]
[T=3]
[B=0]
[R=1]
[CB=1]
[CT=2]
[T=3]
[B=0]
[R=1]
[CB=1]
[CT=3]
[T=3]
[B=0]
[R=1]
[CB=1]
[CT=4]
[T=3]
[B=0]
[R=1]
[CB=1]
[CT=5]
[T=3]
[B=0]
[R=1]
[CB=2]
[CT=0]
[T=3]
[B=0]
[R=1]
[CB=2]
[CT=1]
[T=3]
[B=0]
[R=1]
[CB=2]
[CT=2]
[T=3]
[B=0]
[R=1]
[CB=2]
[CT=3]
[T=3]
[B=0]
[R=1]
[CB=2]
[CT=4]
[T=3]
[B=0]
[R=1]
[CB=2]
[CT=5]
[T=3]
[B=0]
[R=1]
[CB=3]
[CT=0]
[T=3]
[B=0]
[R=1]
[CB=3]
[CT=1]
R180
ct_eob_br
[T=3]
[B=0]
[R=1]
[CB=3]
[CT=2]
[T=3]
[B=0]
[R=1]
[CB=3]
[CT=3]
[T=3]
[B=0]
[R=1]
[CB=3]
[CT=4]
[T=3]
[B=0]
[R=1]
[CB=3]
[CT=5]
[T=3]
[B=0]
[R=1]
[CB=4]
[CT=0]
[T=3]
[B=0]
[R=1]
[CB=4]
[CT=1]
[T=3]
[B=0]
[R=1]
[CB=4]
[CT=2]
[T=3]
[B=0]
[R=1]
[CB=4]
[CT=3]
[T=3]
[B=0]
[R=1]
[CB=4]
[CT=4]
[T=3]
[B=0]
[R=1]
[CB=4]
[CT=5]
[T=3]
[B=0]
[R=1]
[CB=5]
[CT=0]
[T=3]
[B=0]
[R=1]
[CB=5]
[CT=1]
[T=3]
[B=0]
[R=1]
[CB=5]
[CT=2]
[T=3]
[B=0]
[R=1]
[CB=5]
[CT=3]
[T=3]
[B=0]
[R=1]
[CB=5]
[CT=4]
[T=3]
[B=0]
[R=1]
[CB=5]
[CT=5]
R181
ct_eob_br
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
53
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[T=3]
[B=1]
[R=0]
[CB=0]
[CT=0]
[T=3]
[B=1]
[R=0]
[CB=0]
[CT=1]
[T=3]
[B=1]
[R=0]
[CB=0]
[CT=2]
[T=3]
[B=1]
[R=0]
[CB=1]
[CT=0]
[T=3]
[B=1]
[R=0]
[CB=1]
[CT=1]
[T=3]
[B=1]
[R=0]
[CB=1]
[CT=2]
[T=3]
[B=1]
[R=0]
[CB=1]
[CT=3]
[T=3]
[B=1]
[R=0]
[CB=1]
[CT=4]
[T=3]
[B=1]
[R=0]
[CB=1]
[CT=5]
[T=3]
[B=1]
[R=0]
[CB=2]
[CT=0]
[T=3]
[B=1]
[R=0]
[CB=2]
[CT=1]
[T=3]
[B=1]
[R=0]
[CB=2]
[CT=2]
[T=3]
[B=1]
[R=0]
[CB=2]
[CT=3]
[T=3]
[B=1]
[R=0]
[CB=2]
[CT=4]
[T=3]
[B=1]
[R=0]
[CB=2]
[CT=5]
[T=3]
[B=1]
[R=0]
[CB=3]
[CT=0]
R182
ct_eob_br
[T=3]
[B=1]
[R=0]
[CB=3]
[CT=1]
[T=3]
[B=1]
[R=0]
[CB=3]
[CT=2]
[T=3]
[B=1]
[R=0]
[CB=3]
[CT=3]
[T=3]
[B=1]
[R=0]
[CB=3]
[CT=4]
[T=3]
[B=1]
[R=0]
[CB=3]
[CT=5]
[T=3]
[B=1]
[R=0]
[CB=4]
[CT=0]
[T=3]
[B=1]
[R=0]
[CB=4]
[CT=1]
[T=3]
[B=1]
[R=0]
[CB=4]
[CT=2]
[T=3]
[B=1]
[R=0]
[CB=4]
[CT=3]
[T=3]
[B=1]
[R=0]
[CB=4]
[CT=4]
[T=3]
[B=1]
[R=0]
[CB=4]
[CT=5]
[T=3]
[B=1]
[R=0]
[CB=5]
[CT=0]
[T=3]
[B=1]
[R=0]
[CB=5]
[CT=1]
[T=3]
[B=1]
[R=0]
[CB=5]
[CT=2]
[T=3]
[B=1]
[R=0]
[CB=5]
[CT=3]
[T=3]
[B=1]
[R=0]
[CB=5]
[CT=4]
R183
ct_eob_br
[T=3]
[B=1]
[R=0]
[CB=5]
[CT=5]
[T=3]
[B=1]
[R=1]
[CB=0]
[CT=0]
[T=3]
[B=1]
[R=1]
[CB=0]
[CT=1]
[T=3]
[B=1]
[R=1]
[CB=0]
[CT=2]
[T=3]
[B=1]
[R=1]
[CB=1]
[CT=0]
[T=3]
[B=1]
[R=1]
[CB=1]
[CT=1]
[T=3]
[B=1]
[R=1]
[CB=1]
[CT=2]
[T=3]
[B=1]
[R=1]
[CB=1]
[CT=3]
[T=3]
[B=1]
[R=1]
[CB=1]
[CT=4]
[T=3]
[B=1]
[R=1]
[CB=1]
[CT=5]
[T=3]
[B=1]
[R=1]
[CB=2]
[CT=0]
[T=3]
[B=1]
[R=1]
[CB=2]
[CT=1]
[T=3]
[B=1]
[R=1]
[CB=2]
[CT=2]
[T=3]
[B=1]
[R=1]
[CB=2]
[CT=3]
[T=3]
[B=1]
[R=1]
[CB=2]
[CT=4]
[T=3]
[B=1]
[R=1]
[CB=2]
[CT=5]
R184
ct_eob_br
[T=3]
[B=1]
[R=1]
[CB=3]
[CT=0]
[T=3]
[B=1]
[R=1]
[CB=3]
[T=3]
[B=1]
[R=1]
[CB=3]
[T=3]
[B=1]
[R=1]
[CB=3]
[T=3]
[B=1]
[R=1]
[CB=3]
[T=3]
[B=1]
[R=1]
[CB=3]
[T=3]
[B=1]
[R=1]
[CB=4]
[T=3]
[B=1]
[R=1]
[CB=4]
[T=3]
[B=1]
[R=1]
[CB=4]
[T=3]
[B=1]
[R=1]
[CB=4]
[T=3]
[B=1]
[R=1]
[CB=4]
[T=3]
[B=1]
[R=1]
[CB=4]
[T=3]
[B=1]
[R=1]
[CB=5]
[T=3]
[B=1]
[R=1]
[CB=5]
[T=3]
[B=1]
[R=1]
[CB=5]
[T=3]
[B=1]
[R=1]
[CB=5]
[CT=3]
HEVC
54
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[CT=1]
[CT=2]
[CT=3]
[CT=4]
[CT=5]
[CT=0]
[CT=1]
[CT=2]
[CT=3]
[CT=4]
[CT=5]
[CT=0]
[CT=1]
[CT=2]
R185
ct_eob_br
ct_uv_mode
[T=3]
[B=1]
[R=1]
[CB=5]
[CT=4]
[T=3]
[B=1]
[R=1]
[CB=5]
[CT=5]
[0]
[0]
[0]
[1]
[0]
[2]
[0]
[3]
[0]
[4]
[0]
[5]
[0]
[6]
[0]
[7]
[0]
[8]
[0]
[9]
[1]
[0]
[1]
[1]
[1]
[2]
[1]
[3]
R186
ct_uv_mode
[1]
[4]
[1]
[5]
[1]
[6]
[1]
[7]
[1]
[8]
[1]
[9]
[2]
[0]
[2]
[1]
[2]
[2]
[2]
[3]
[2]
[4]
[2]
[5]
[2]
[6]
[2]
[7]
[2]
[8]
[2]
[9]
R187
ct_uv_mode
[3]
[0]
[3]
[1]
[3]
[2]
[3]
[3]
[3]
[4]
[3]
[5]
[3]
[6]
[3]
[7]
[3]
[8]
[3]
[9]
[4]
[0]
[4]
[1]
[4]
[2]
[4]
[3]
[4]
[4]
[4]
[5]
R188
ct_uv_mode
[4]
[6]
[4]
[7]
[4]
[8]
[4]
[9]
[5]
[0]
[5]
[1]
[5]
[2]
[5]
[3]
[5]
[4]
[5]
[5]
[5]
[6]
[5]
[7]
[5]
[8]
[5]
[9]
[6]
[0]
[6]
[1]
R189
ct_uv_mode
[6]
[2]
[6]
[3]
[6]
[4]
[6]
[5]
[6]
[6]
[6]
[7]
[6]
[8]
[6]
[9]
[7]
[0]
[7]
[1]
[7]
[2]
[7]
[3]
[7]
[4]
[7]
[5]
[7]
[6]
[7]
[7]
R190
ct_uv_mode
[7]
[8]
[7]
[9]
[8]
[0]
[8]
[1]
[8]
[2]
[8]
[3]
[8]
[4]
[8]
[5]
[8]
[6]
[8]
[7]
[8]
[8]
[8]
[9]
[9]
[0]
[9]
[1]
[9]
[2]
[9]
[3]
R191
ct_uv_mode
ct_seg_id
ct_seg_pred
[9]
[9]
[9]
[9]
[9]
[9]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[0]
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
55
Rxxx Value
1 row = 1
Cacheline
16 32-bit counters
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[4]
[5]
[6]
[7]
[8]
[9]
[0]
[1]
R192
ct_seg_pred
[1]
[0]
[1]
[1]
[2]
[0]
[2]
[1]
Probability Statistics Counters Context Legend
Counter
i
j
k
l
m
n
Dimension
Total
Number
of
Counters
ct_tx_8x8
Context
Node
2X2
4
[i]
[j]
ct_tx_16x16
Context
Node
2X3
6
[i]
[j]
ct_tx_32x32
Context
Node
2X4
8
[i]
[j]
ct_coef
T = TransformSize (0 4x4,
1 8x8, 2 16x16, 3 32x32)
B = BlockType (0 Y, 1
UV)
R =
ReferenceType
(0 Intra, 1
Inter)
CB =
CoefficientBand
CT =
Context
N =
Node
(0
ZERO,
1
ONE,
2
TWO,
3
4X2X2X6X6X4
2112
[T=i]
[B=j]
[R=k]
[CB=l]
[CT=m]
[N=n]
HEVC
56
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Counter
i
j
k
l
m
n
Dimension
Total
Number
of
Counters
EOB)
ct_mbskip
Context
Node
3X2
6
[i]
[j]
ct_inter_mode
Context (BOTH_ZERO,
ZERO_PLUS_PREDICTED,
BOTH_PREDICTED,
NEW_PLUS_NON_INTRA,
BOTH_NEW,
INTRA_PLUS_NON_INTRA,
BOTH_INTRA)
Node (NEARESTMV,
NEARMV, ZEROMV,
NEWMV)
7X4
28
[i]
[j]
ct_switchable_interp
Context
Node
(MV_JOINT_ZERO,
MV_JOINT_HNZVZ,
MV_JOINT_HZVNZ,
MV_JOINT_HNZVNZ)
3X4
12
[i]
[j]
ct_intra_inter
Context
Node
4X2
8
[i]
[j]
ct_comp_inter
Context
Node
5X2
10
[i]
[j]
ct_single_ref
P0,P1
Context
Node
2X5X2
20
[i]
[j]
[k]
ct_comp_ref
Context
Node
5X2
10
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
57
Counter
i
j
k
l
m
n
Dimension
Total
Number
of
Counters
[i]
[j]
ct_y_mode
BLOCK_SIZE_GROUPS
Node (DC_PRED,
TM_PRED, V_PRED,
H_PRED, D135_PRED,
D117_PRED,
D45_PRED,
D63_PRED,
D153_PRED,
D27_PRED)
4x10
40
[i]
[j]
ct_partition
Context
Node (00: NONE, 01:
HORZ, 10: VERT, 11:
SPLIT)
16X4
64
[i]
[j]
ct_mv_joints
Node (MV_JOINT_ZERO,
MV_JOINT_HNZVZ,
MV_JOINT_HZVNZ,
MV_JOINT_HNZVNZ)
4
4
[i]
ct_mv_sign
XY
Node
2X2
4
[i]
[j]
ct_mv_classes
XY
MV CLASS
2X10
20
[i]
[j]
ct_mv_class0
XY
Node
2X2
4
[i]
[j]
ct_mv_bits
XY
MV BIT POSITION
Node
2X10X2
40
HEVC
58
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Counter
i
j
k
l
m
n
Dimension
Total
Number
of
Counters
[i]
[j]
[k]
ct_mv_class0_fp
XY
MV_CLASS0 BIT
Node
2X2X4
16
[i]
[j]
[k]
ct_mv_fp
XY
Node
2X4
8
[i]
[j]
ct_mv_class0_hp
XY
Node
2X2
4
[i]
[j]
ct_mv_hp
XY
Node
2X2
4
[i]
[j]
ct_eob_br
T = TransformSize (0 4x4,
1 8x8, 2 16x16, 3 32x32)
B = BlockType (0 Y, 1
UV)
R =
ReferenceType
(0 Intra, 1
Inter)
CB =
CoefficientBand
CT =
Context
4X2X2X6X6
528
[T=i]
[B=j]
[R=k]
[CB=l]
[CT=m]
ct_uv_mode
Context
Node(DC_PRED,
TM_PRED, V_PRED,
H_PRED, D135_PRED,
D117_PRED,
D45_PRED,
10x10
100
[i]
[j]
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
59
Counter
i
j
k
l
m
n
Dimension
Total
Number
of
Counters
D63_PRED,
D153_PRED,
D27_PRED)
ct_seg_id[i]
Node
8
8
[i]
ct_seg_pred
Context
Node
3X2
6
[i]
[j]
3074
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
1
VP9 PAK Quant Lookup Tables
Qinde
x
IQ_Scale
FQ_Shift
FQ_Quant
8b
10b
12b
8b
10b
12b
8b
10b
12b
DC
AC
DC
AC
DC
AC
D
C
A
C
D
C
A
C
D
C
A
C
DC
AC
DC
AC
DC
AC
0
4
4
4
4
4
4
1
1
1
1
1
1
3276
8
3276
8
3276
8
3276
8
3276
8
3276
8
1
8
8
9
9
12
13
2
2
2
2
2
2
3276
8
3276
8
2912
7
2912
7
2184
5
2016
4
2
8
9
10
11
18
19
2
2
2
2
3
3
3276
8
2912
7
2621
4
2383
1
2912
7
2759
4
3
9
10
13
13
25
27
2
2
2
2
3
3
2912
7
2621
4
2016
4
2016
4
2097
1
1941
8
4
10
11
15
16
33
35
2
2
2
3
4
4
2621
4
2383
1
1747
6
3276
8
3177
5
2995
9
5
11
12
17
18
41
44
2
2
3
3
4
4
2383
1
2184
5
3084
0
2912
7
2557
5
2383
1
6
12
13
20
21
50
54
2
2
3
3
4
4
2184
5
2016
4
2621
4
2496
6
2097
1
1941
8
7
12
14
22
24
60
64
2
2
3
3
4
5
2184
5
1872
4
2383
1
2184
5
1747
6
3276
8
8
13
15
25
27
70
75
2
2
3
3
5
5
2016
4
1747
6
2097
1
1941
8
2995
9
2796
2
9
14
16
28
30
80
87
2
3
3
3
5
5
1872
4
3276
8
1872
4
1747
6
2621
4
2410
5
10
15
17
31
33
91
99
2
3
3
4
5
5
1747
6
3084
0
1691
2
3177
5
2304
5
2118
3
11
16
18
34
37
103
112
3
3
4
4
5
5
3276
8
2912
7
3084
0
2833
9
2036
0
1872
4
12
17
19
37
40
115
126
3
3
4
4
5
5
3084
0
2759
4
2833
9
2621
4
1823
6
1664
4
13
18
20
40
44
127
139
3
3
4
4
5
6
2912
7
2621
4
2621
4
2383
1
1651
3
3017
4
14
19
21
43
48
140
154
3
3
4
4
6
6
2759
4
2496
6
2438
5
2184
5
2995
9
2723
5
15
19
22
47
51
153
168
3
3
4
4
6
6
2759
4
2383
1
2231
0
2056
0
2741
3
2496
6
16
20
23
50
55
166
183
3
3
4
4
6
6
2621
4
2279
5
2097
1
1906
5
2526
6
2291
9
17
21
24
53
59
180
199
3
3
4
4
6
6
2496
6
2184
5
1978
4
1777
2
2330
1
2107
6
HEVC
2
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Qinde
x
IQ_Scale
FQ_Shift
FQ_Quant
8b
10b
12b
8b
10b
12b
8b
10b
12b
DC
AC
DC
AC
DC
AC
D
C
A
C
D
C
A
C
D
C
A
C
DC
AC
DC
AC
DC
AC
18
22
25
57
63
194
214
3
3
4
4
6
6
2383
1
2097
1
1839
6
1664
4
2162
0
1959
9
19
23
26
60
67
208
230
3
3
4
5
6
6
2279
5
2016
4
1747
6
3130
0
2016
4
1823
6
20
24
27
64
71
222
247
3
3
5
5
6
6
2184
5
1941
8
3276
8
2953
7
1889
3
1698
0
21
25
28
68
75
237
263
3
3
5
5
6
7
2097
1
1872
4
3084
0
2796
2
1769
7
3189
5
22
26
29
71
79
251
280
3
3
5
5
6
7
2016
4
1807
8
2953
7
2654
6
1671
0
2995
9
23
26
30
75
83
266
297
3
3
5
5
7
7
2016
4
1747
6
2796
2
2526
6
3153
6
2824
4
24
27
31
78
88
281
314
3
3
5
5
7
7
1941
8
1691
2
2688
6
2383
1
2985
2
2671
5
25
28
32
82
92
296
331
3
4
5
5
7
7
1872
4
3276
8
2557
5
2279
5
2833
9
2534
3
26
29
33
86
96
312
349
3
4
5
5
7
7
1807
8
3177
5
2438
5
2184
5
2688
6
2403
6
27
30
34
90
100
327
366
3
4
5
5
7
7
1747
6
3084
0
2330
1
2097
1
2565
3
2291
9
28
31
35
93
105
343
384
3
4
5
5
7
7
1691
2
2995
9
2255
0
1997
2
2445
6
2184
5
29
32
36
97
109
358
402
4
4
5
5
7
7
3276
8
2912
7
2162
0
1923
9
2343
1
2086
7
30
32
37
101
114
374
420
4
4
5
5
7
7
3276
8
2833
9
2076
3
1839
6
2242
9
1997
2
31
33
38
105
118
390
438
4
4
5
5
7
7
3177
5
2759
4
1997
2
1777
2
2150
9
1915
2
32
34
39
109
122
405
456
4
4
5
5
7
7
3084
0
2688
6
1923
9
1718
9
2071
2
1839
6
33
35
40
113
127
421
475
4
4
5
5
7
7
2995
9
2621
4
1855
8
1651
3
1992
5
1766
0
34
36
41
116
131
437
493
4
4
5
6
7
7
2912
7
2557
5
1807
8
3201
7
1919
5
1701
5
35
37
42
120
136
453
511
4
4
5
6
7
7
2833
9
2496
6
1747
6
3084
0
1851
7
1641
6
36
38
43
124
140
469
530
4
4
5
6
7
8
2759
2438
1691
2995
1788
3165
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
3
Qinde
x
IQ_Scale
FQ_Shift
FQ_Quant
8b
10b
12b
8b
10b
12b
8b
10b
12b
DC
AC
DC
AC
DC
AC
D
C
A
C
D
C
A
C
D
C
A
C
DC
AC
DC
AC
DC
AC
4
5
2
9
6
5
37
38
44
128
145
484
548
4
4
6
6
7
8
2759
4
2383
1
3276
8
2892
6
1733
1
3061
5
38
39
45
132
149
500
567
4
4
6
6
7
8
2688
6
2330
1
3177
5
2814
9
1677
7
2958
9
39
40
46
136
154
516
586
4
4
6
6
8
8
2621
4
2279
5
3084
0
2723
5
3251
3
2863
0
40
41
47
140
158
532
604
4
4
6
6
8
8
2557
5
2231
0
2995
9
2654
6
3153
6
2777
6
41
42
48
143
163
548
623
4
4
6
6
8
8
2496
6
2184
5
2933
0
2573
1
3061
5
2692
9
42
43
49
147
168
564
642
4
4
6
6
8
8
2438
5
2139
9
2853
2
2496
6
2974
6
2613
2
43
43
50
151
172
580
660
4
4
6
6
8
8
2438
5
2097
1
2777
6
2438
5
2892
6
2542
0
44
44
51
155
177
596
679
4
4
6
6
8
8
2383
1
2056
0
2706
0
2369
6
2814
9
2470
8
45
45
52
159
181
611
698
4
4
6
6
8
8
2330
1
2016
4
2637
9
2317
2
2745
8
2403
6
46
46
53
163
186
627
716
4
4
6
6
8
8
2279
5
1978
4
2573
1
2255
0
2675
7
2343
1
47
47
54
166
190
643
735
4
4
6
6
8
8
2231
0
1941
8
2526
6
2207
5
2609
2
2282
6
48
48
55
170
195
659
753
4
4
6
6
8
8
2184
5
1906
5
2467
2
2150
9
2545
8
2228
0
49
48
56
174
199
674
772
4
4
6
6
8
8
2184
5
1872
4
2410
5
2107
6
2489
2
2173
2
50
49
57
178
204
690
791
4
4
6
6
8
8
2139
9
1839
6
2356
3
2056
0
2431
4
2121
0
51
50
58
182
208
706
809
4
4
6
6
8
8
2097
1
1807
8
2304
5
2016
4
2376
3
2073
8
52
51
59
185
213
721
828
4
4
6
6
8
8
2056
0
1777
2
2267
1
1969
1
2326
9
2026
2
53
52
60
189
217
737
846
4
4
6
6
8
8
2016
4
1747
6
2219
2
1932
8
2276
4
1983
1
54
53
61
193
222
752
865
4
4
6
6
8
8
1978
4
1718
9
2173
2
1889
3
2231
0
1939
5
HEVC
4
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Qinde
x
IQ_Scale
FQ_Shift
FQ_Quant
8b
10b
12b
8b
10b
12b
8b
10b
12b
DC
AC
DC
AC
DC
AC
D
C
A
C
D
C
A
C
D
C
A
C
DC
AC
DC
AC
DC
AC
55
53
62
197
226
768
884
4
4
6
6
8
8
1978
4
1691
2
2129
0
1855
8
2184
5
1897
8
56
54
63
200
231
783
902
4
4
6
6
8
8
1941
8
1664
4
2097
1
1815
7
2142
6
1860
0
57
55
64
204
235
798
920
4
5
6
6
8
8
1906
5
3276
8
2056
0
1784
8
2102
4
1823
6
58
56
65
208
240
814
939
4
5
6
6
8
8
1872
4
3226
3
2016
4
1747
6
2061
0
1786
7
59
57
66
212
244
829
957
4
5
6
6
8
8
1839
6
3177
5
1978
4
1718
9
2023
7
1753
1
60
57
67
215
249
844
976
4
5
6
6
8
8
1839
6
3130
0
1950
8
1684
4
1987
8
1718
9
61
58
68
219
253
859
994
4
5
6
6
8
8
1807
8
3084
0
1915
2
1657
8
1953
1
1687
8
62
59
69
223
258
874
1012
4
5
6
7
8
8
1777
2
3039
3
1880
8
3251
3
1919
5
1657
8
63
60
70
226
262
889
1030
4
5
6
7
8
9
1747
6
2995
9
1855
8
3201
7
1887
2
3257
7
64
61
71
230
267
904
1049
4
5
6
7
8
9
1718
9
2953
7
1823
6
3141
8
1855
8
3198
7
65
62
72
233
271
919
1067
4
5
6
7
8
9
1691
2
2912
7
1800
1
3095
4
1825
5
3144
7
66
62
73
237
275
934
1085
4
5
6
7
8
9
1691
2
2872
8
1769
7
3050
4
1796
2
3092
5
67
63
74
241
280
949
1103
4
5
6
7
8
9
1664
4
2833
9
1740
3
2995
9
1767
8
3042
1
68
64
75
244
284
964
1121
5
5
6
7
8
9
3276
8
2796
2
1718
9
2953
7
1740
3
2993
2
69
65
76
248
289
978
1139
5
5
6
7
8
9
3226
3
2759
4
1691
2
2902
6
1715
4
2945
9
70
66
77
251
293
993
1157
5
5
6
7
8
9
3177
5
2723
5
1671
0
2863
0
1689
5
2900
1
71
66
78
255
297
1008
1175
5
5
6
7
8
9
3177
5
2688
6
1644
8
2824
4
1664
4
2855
6
72
67
79
259
302
1022
1193
5
5
7
7
8
9
3130
0
2654
6
3238
8
2777
6
1641
6
2812
6
73
68
80
262
306
1037
1211
5
5
7
7
9
9
3084
2621
3201
2741
3235
2770
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
5
Qinde
x
IQ_Scale
FQ_Shift
FQ_Quant
8b
10b
12b
8b
10b
12b
8b
10b
12b
DC
AC
DC
AC
DC
AC
D
C
A
C
D
C
A
C
D
C
A
C
DC
AC
DC
AC
DC
AC
0
4
7
3
7
8
74
69
81
266
311
1051
1229
5
5
7
7
9
9
3039
3
2589
0
3153
6
2697
3
3192
6
2730
2
75
70
82
269
315
1065
1246
5
5
7
7
9
9
2995
9
2557
5
3118
4
2663
0
3150
6
2692
9
76
70
83
273
319
1080
1264
5
5
7
7
9
9
2995
9
2526
6
3072
7
2629
6
3106
8
2654
6
77
71
84
276
324
1094
1282
5
5
7
7
9
9
2953
7
2496
6
3039
3
2589
0
3067
1
2617
3
78
72
85
280
328
1108
1299
5
5
7
7
9
9
2912
7
2467
2
2995
9
2557
5
3028
3
2583
0
79
73
86
283
332
1122
1317
5
5
7
7
9
9
2872
8
2438
5
2964
1
2526
6
2990
5
2547
7
80
74
87
287
337
1136
1335
5
5
7
7
9
9
2833
9
2410
5
2922
8
2489
2
2953
7
2513
4
81
74
88
290
341
1151
1352
5
5
7
7
9
9
2833
9
2383
1
2892
6
2460
0
2915
2
2481
8
82
75
89
293
345
1165
1370
5
5
7
7
9
9
2796
2
2356
3
2863
0
2431
4
2880
2
2449
2
83
76
90
297
349
1179
1387
5
5
7
7
9
9
2759
4
2330
1
2824
4
2403
6
2846
0
2419
2
84
77
91
300
354
1192
1405
5
5
7
7
9
9
2723
5
2304
5
2796
2
2369
6
2814
9
2388
2
85
78
92
304
358
1206
1422
5
5
7
7
9
9
2688
6
2279
5
2759
4
2343
1
2782
2
2359
6
86
78
93
307
362
1220
1440
5
5
7
7
9
9
2688
6
2255
0
2732
4
2317
2
2750
3
2330
1
87
79
94
310
367
1234
1457
5
5
7
7
9
9
2654
6
2231
0
2706
0
2285
7
2719
1
2302
9
88
80
95
314
371
1248
1474
5
5
7
7
9
9
2621
4
2207
5
2671
5
2261
0
2688
6
2276
4
89
81
96
317
375
1261
1491
5
5
7
7
9
9
2589
0
2184
5
2646
2
2236
9
2660
9
2250
4
90
81
97
321
379
1275
1509
5
5
7
7
9
9
2589
0
2162
0
2613
2
2213
3
2631
7
2223
6
91
82
98
324
384
1288
1526
5
5
7
7
9
9
2557
5
2139
9
2589
0
2184
5
2605
1
2198
8
HEVC
6
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Qinde
x
IQ_Scale
FQ_Shift
FQ_Quant
8b
10b
12b
8b
10b
12b
8b
10b
12b
DC
AC
DC
AC
DC
AC
D
C
A
C
D
C
A
C
D
C
A
C
DC
AC
DC
AC
DC
AC
92
83
99
327
388
1302
1543
5
5
7
7
9
9
2526
6
2118
3
2565
3
2162
0
2577
1
2174
6
93
84
100
331
392
1315
1560
5
5
7
7
9
9
2496
6
2097
1
2534
3
2139
9
2551
6
2150
9
94
85
101
334
396
1329
1577
5
5
7
7
9
9
2467
2
2076
3
2511
5
2118
3
2524
7
2127
7
95
85
102
337
401
1342
1595
5
5
7
7
9
9
2467
2
2056
0
2489
2
2091
9
2500
3
2103
7
96
87
104
343
409
1368
1627
5
5
7
7
9
9
2410
5
2016
4
2445
6
2051
0
2452
8
2062
3
97
88
106
350
417
1393
1660
5
5
7
7
9
9
2383
1
1978
4
2396
7
2011
6
2408
7
2021
3
98
90
108
356
425
1419
1693
5
5
7
7
9
9
2330
1
1941
8
2356
3
1973
7
2364
6
1981
9
99
92
110
362
433
1444
1725
5
5
7
7
9
9
2279
5
1906
5
2317
2
1937
3
2323
7
1945
1
100
93
112
369
441
1469
1758
5
5
7
7
9
9
2255
0
1872
4
2273
3
1902
1
2284
1
1908
6
101
95
114
375
449
1494
1791
5
5
7
7
9
9
2207
5
1839
6
2236
9
1868
2
2245
9
1873
5
102
96
116
381
458
1519
1824
5
5
7
7
9
9
2184
5
1807
8
2201
7
1831
5
2208
9
1839
6
103
98
118
387
466
1544
1856
5
5
7
7
9
9
2139
9
1777
2
2167
5
1800
1
2173
2
1807
8
104
99
120
394
474
1569
1889
5
5
7
7
9
9
2118
3
1747
6
2129
0
1769
7
2138
5
1776
3
105
101
122
400
482
1594
1922
5
5
7
7
9
9
2076
3
1718
9
2097
1
1740
3
2105
0
1745
8
106
102
124
406
490
1618
1954
5
5
7
7
9
9
2056
0
1691
2
2066
1
1711
9
2073
8
1717
2
107
104
126
412
498
1643
1987
5
5
7
7
9
9
2016
4
1664
4
2036
0
1684
4
2042
2
1688
6
108
105
128
418
506
1668
2020
5
6
7
7
9
9
1997
2
3276
8
2006
8
1657
8
2011
6
1661
1
109
107
130
424
514
1692
2052
5
6
7
8
9
10
1959
9
3226
3
1978
4
3264
0
1983
1
3270
4
110
108
132
430
523
1717
2085
5
6
7
8
9
10
1941
3177
1950
3207
1954
3218
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
7
Qinde
x
IQ_Scale
FQ_Shift
FQ_Quant
8b
10b
12b
8b
10b
12b
8b
10b
12b
DC
AC
DC
AC
DC
AC
D
C
A
C
D
C
A
C
D
C
A
C
DC
AC
DC
AC
DC
AC
8
5
8
8
2
6
111
110
134
436
531
1741
2118
5
6
7
8
9
10
1906
5
3130
0
1923
9
3159
5
1927
3
3168
5
112
111
136
442
539
1765
2150
5
6
7
8
9
10
1889
3
3084
0
1897
8
3112
6
1901
1
3121
3
113
113
138
448
547
1789
2183
5
6
7
8
9
10
1855
8
3039
3
1872
4
3067
1
1875
5
3074
1
114
114
140
454
555
1814
2216
5
6
7
8
9
10
1839
6
2995
9
1847
7
3022
9
1849
7
3028
3
115
116
142
460
563
1838
2248
5
6
7
8
9
10
1807
8
2953
7
1823
6
2979
9
1825
5
2985
2
116
117
144
466
571
1862
2281
5
6
7
8
9
10
1792
4
2912
7
1800
1
2938
2
1802
0
2942
0
117
118
146
472
579
1885
2313
5
6
7
8
9
10
1777
2
2872
8
1777
2
2897
6
1780
0
2901
3
118
120
148
478
588
1909
2346
5
6
7
8
9
10
1747
6
2833
9
1754
9
2853
2
1757
6
2860
5
119
121
150
484
596
1933
2378
5
6
7
8
9
10
1733
1
2796
2
1733
1
2814
9
1735
8
2822
0
120
123
152
490
604
1957
2411
5
6
7
8
9
10
1705
0
2759
4
1711
9
2777
6
1714
5
2783
4
121
125
155
499
616
1992
2459
5
6
7
8
9
10
1677
7
2706
0
1681
0
2723
5
1684
4
2729
1
122
127
158
507
628
2027
2508
5
6
7
8
9
10
1651
3
2654
6
1654
5
2671
5
1655
3
2675
7
123
129
161
516
640
2061
2556
6
6
8
8
10
10
3251
3
2605
1
3251
3
2621
4
3256
1
2625
5
124
131
164
525
652
2096
2605
6
6
8
8
10
10
3201
7
2557
5
3195
6
2573
1
3201
7
2576
1
125
134
167
533
664
2130
2653
6
6
8
8
10
10
3130
0
2511
5
3147
6
2526
6
3150
6
2529
5
126
136
170
542
676
2165
2701
6
6
8
8
10
10
3084
0
2467
2
3095
4
2481
8
3099
7
2484
5
127
138
173
550
688
2199
2750
6
6
8
8
10
10
3039
3
2424
4
3050
4
2438
5
3051
7
2440
3
128
140
176
559
700
2233
2798
6
6
8
8
10
10
2995
9
2383
1
3001
2
2396
7
3005
3
2398
4
HEVC
8
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Qinde
x
IQ_Scale
FQ_Shift
FQ_Quant
8b
10b
12b
8b
10b
12b
8b
10b
12b
DC
AC
DC
AC
DC
AC
D
C
A
C
D
C
A
C
D
C
A
C
DC
AC
DC
AC
DC
AC
129
142
179
567
713
2267
2847
6
6
8
8
10
10
2953
7
2343
1
2958
9
2353
0
2960
2
2357
1
130
144
182
576
725
2300
2895
6
6
8
8
10
10
2912
7
2304
5
2912
7
2314
0
2917
7
2318
0
131
146
185
584
737
2334
2943
6
6
8
8
10
10
2872
8
2267
1
2872
8
2276
4
2875
2
2280
2
132
148
188
592
749
2367
2992
6
6
8
8
10
10
2833
9
2231
0
2833
9
2239
9
2835
1
2242
9
133
150
191
601
761
2400
3040
6
6
8
8
10
10
2796
2
2195
9
2791
5
2204
6
2796
2
2207
5
134
152
194
609
773
2434
3088
6
6
8
8
10
10
2759
4
2162
0
2754
8
2170
4
2757
1
2173
2
135
154
197
617
785
2467
3137
6
6
8
8
10
10
2723
5
2129
0
2719
1
2137
2
2720
2
2139
2
136
156
200
625
797
2499
3185
6
6
8
8
10
10
2688
6
2097
1
2684
3
2105
0
2685
4
2107
0
137
158
203
634
809
2532
3234
6
6
8
8
10
10
2654
6
2066
1
2646
2
2073
8
2650
4
2075
1
138
161
207
644
825
2575
3298
6
6
8
8
10
10
2605
1
2026
2
2605
1
2033
6
2606
1
2034
8
139
164
211
655
841
2618
3362
6
6
8
8
10
10
2557
5
1987
8
2561
4
1994
9
2563
3
1996
0
140
166
215
666
857
2661
3426
6
6
8
8
10
10
2526
6
1950
8
2519
1
1957
6
2521
9
1958
8
141
169
219
676
873
2704
3491
6
6
8
8
10
10
2481
8
1915
2
2481
8
1921
7
2481
8
1922
3
142
172
223
687
889
2746
3555
6
6
8
8
10
10
2438
5
1880
8
2442
0
1887
2
2443
8
1887
7
143
174
227
698
905
2788
3619
6
6
8
8
10
10
2410
5
1847
7
2403
6
1853
8
2407
0
1854
3
144
177
231
708
922
2830
3684
6
6
8
8
10
10
2369
6
1815
7
2369
6
1819
6
2371
3
1821
6
145
180
235
718
938
2872
3748
6
6
8
8
10
10
2330
1
1784
8
2336
6
1788
6
2336
6
1790
5
146
182
239
729
954
2913
3812
6
6
8
8
10
10
2304
5
1754
9
2301
4
1758
6
2303
7
1760
4
147
185
243
739
970
2954
3876
6
6
8
8
10
10
2267
1726
2270
1729
2271
1731
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
9
Qinde
x
IQ_Scale
FQ_Shift
FQ_Quant
8b
10b
12b
8b
10b
12b
8b
10b
12b
DC
AC
DC
AC
DC
AC
D
C
A
C
D
C
A
C
D
C
A
C
DC
AC
DC
AC
DC
AC
1
0
2
6
7
3
148
187
247
749
986
2995
3941
6
6
8
8
10
10
2242
9
1698
0
2239
9
1701
5
2240
6
1702
8
149
190
251
759
100
2
3036
4005
6
6
8
8
10
10
2207
5
1671
0
2210
4
1674
3
2210
4
1675
6
150
192
255
770
101
8
3076
4069
6
6
8
8
10
10
2184
5
1644
8
2178
8
1648
0
2181
6
1649
2
151
195
260
782
103
8
3127
4149
6
7
8
9
10
11
2150
9
3226
3
2145
4
3232
6
2146
1
3234
9
152
199
265
795
105
8
3177
4230
6
7
8
9
10
11
2107
6
3165
5
2110
3
3171
4
2112
3
3172
9
153
202
270
807
107
8
3226
4310
6
7
8
9
10
11
2076
3
3106
8
2078
9
3112
6
2080
2
3114
1
154
205
275
819
109
8
3275
4390
6
7
8
9
10
11
2046
0
3050
4
2048
5
3055
9
2049
1
3057
3
155
208
280
831
111
8
3324
4470
6
7
8
9
10
11
2016
4
2995
9
2018
9
3001
2
2018
9
3002
6
156
211
285
844
113
8
3373
4550
6
7
8
9
10
11
1987
8
2943
3
1987
8
2948
5
1989
5
2949
8
157
214
290
856
115
8
3421
4631
6
7
8
9
10
11
1959
9
2892
6
1959
9
2897
6
1961
6
2898
2
158
217
295
868
117
8
3469
4711
6
7
8
9
10
11
1932
8
2843
5
1932
8
2848
4
1934
5
2849
0
159
220
300
880
119
8
3517
4791
6
7
8
9
10
11
1906
5
2796
2
1906
5
2800
8
1908
1
2801
4
160
223
305
891
121
8
3565
4871
6
7
8
9
10
11
1880
8
2750
3
1882
9
2754
8
1882
4
2755
4
161
226
311
906
124
2
3621
4967
6
7
8
9
10
11
1855
8
2697
3
1851
7
2701
6
1853
3
2702
1
162
230
317
920
126
6
3677
5064
6
7
8
9
10
11
1823
6
2646
2
1823
6
2650
4
1825
0
2650
4
163
233
323
933
129
0
3733
5160
6
7
8
9
10
11
1800
1
2597
0
1798
2
2601
1
1797
7
2601
1
164
237
329
947
131
4
3788
5256
6
7
8
9
10
11
1769
7
2549
7
1771
6
2553
6
1771
6
2553
6
165
240
335
961
133
8
3843
5352
6
7
8
9
10
11
1747
6
2504
0
1745
8
2507
8
1746
2
2507
8
HEVC
10
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Qinde
x
IQ_Scale
FQ_Shift
FQ_Quant
8b
10b
12b
8b
10b
12b
8b
10b
12b
DC
AC
DC
AC
DC
AC
D
C
A
C
D
C
A
C
D
C
A
C
DC
AC
DC
AC
DC
AC
166
243
341
975
136
2
3897
5448
6
7
8
9
10
11
1726
0
2460
0
1720
7
2463
6
1722
0
2463
6
167
247
347
988
138
6
3951
5544
6
7
8
9
10
11
1698
0
2417
4
1698
0
2420
9
1698
5
2420
9
168
250
353
100
1
141
1
4005
5641
6
7
8
9
10
11
1677
7
2376
3
1676
0
2378
0
1675
6
2379
3
169
253
359
101
5
143
5
4058
5737
6
7
8
9
10
11
1657
8
2336
6
1652
9
2338
2
1653
7
2339
5
170
257
366
103
0
146
3
4119
5849
7
7
9
9
11
11
3264
0
2291
9
3257
7
2293
5
3258
5
2294
7
171
261
373
104
5
149
1
4181
5961
7
7
9
9
11
11
3214
0
2248
9
3210
9
2250
4
3210
1
2251
5
172
265
380
106
1
151
9
4241
6073
7
7
9
9
11
11
3165
5
2207
5
3162
5
2208
9
3164
7
2210
0
173
269
387
107
6
154
7
4301
6185
7
7
9
9
11
11
3118
4
2167
5
3118
4
2169
0
3120
6
2170
0
174
272
394
109
0
157
5
4361
6297
7
7
9
9
11
11
3084
0
2129
0
3078
3
2130
4
3077
6
2131
4
175
276
401
110
5
160
3
4420
6410
7
7
9
9
11
11
3039
3
2091
9
3036
6
2093
2
3036
6
2093
8
176
280
408
112
0
163
1
4479
6522
7
7
9
9
11
11
2995
9
2056
0
2995
9
2057
2
2996
6
2057
9
177
284
416
113
7
166
3
4546
6650
7
7
9
9
11
11
2953
7
2016
4
2951
1
2017
7
2952
4
2018
3
178
288
424
115
3
169
5
4612
6778
7
7
9
9
11
11
2912
7
1978
4
2910
1
1979
6
2910
1
1980
1
179
292
432
117
0
172
7
4677
6906
7
7
9
9
11
11
2872
8
1941
8
2867
9
1942
9
2869
7
1943
4
180
296
440
118
6
175
9
4742
7034
7
7
9
9
11
11
2833
9
1906
5
2829
2
1907
5
2830
4
1908
1
181
300
448
120
2
179
1
4807
7162
7
7
9
9
11
11
2796
2
1872
4
2791
5
1873
5
2792
1
1874
0
182
304
456
121
8
182
3
4871
7290
7
7
9
9
11
11
2759
4
1839
6
2754
8
1840
6
2755
4
1841
1
183
309
465
123
6
185
9
4942
7435
7
7
9
9
11
11
2714
7
1804
0
2714
7
1804
9
2715
8
1805
2
184
313
474
125
189
5013
7579
7
7
9
9
11
11
2680
1769
2677
1770
2677
1770
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
11
Qinde
x
IQ_Scale
FQ_Shift
FQ_Quant
8b
10b
12b
8b
10b
12b
8b
10b
12b
DC
AC
DC
AC
DC
AC
D
C
A
C
D
C
A
C
D
C
A
C
DC
AC
DC
AC
DC
AC
3
5
0
7
9
6
3
9
185
317
483
127
1
193
1
5083
7723
7
7
9
9
11
11
2646
2
1736
7
2640
0
1737
6
2640
5
1737
8
186
322
492
128
8
196
7
5153
7867
7
7
9
9
11
11
2605
1
1705
0
2605
1
1705
8
2604
6
1706
0
187
326
501
130
6
200
3
5222
8011
7
7
9
9
11
11
2573
1
1674
3
2569
2
1675
2
2570
2
1675
4
188
330
510
132
3
203
9
5291
8155
7
7
9
9
11
11
2542
0
1644
8
2536
2
1645
6
2536
7
1645
8
189
335
520
134
2
207
9
5367
8315
7
8
9
10
11
12
2504
0
3226
3
2500
3
3227
9
2500
7
3228
3
190
340
530
136
1
211
9
5442
8475
7
8
9
10
11
12
2467
2
3165
5
2465
4
3167
0
2466
3
3167
3
191
344
540
137
9
215
9
5517
8635
7
8
9
10
11
12
2438
5
3106
8
2433
2
3108
3
2432
8
3108
6
192
349
550
139
8
219
9
5591
8795
7
8
9
10
11
12
2403
6
3050
4
2400
1
3051
7
2400
6
3052
1
193
354
560
141
6
223
9
5665
8956
7
8
9
10
11
12
2369
6
2995
9
2369
6
2997
2
2369
2
2997
2
194
359
571
143
6
228
3
5745
9132
7
8
9
10
11
12
2336
6
2938
2
2336
6
2939
5
2336
2
2939
5
195
364
582
145
6
232
7
5825
9308
7
8
9
10
11
12
2304
5
2882
6
2304
5
2883
9
2304
1
2883
9
196
369
593
147
6
237
1
5905
9484
7
8
9
10
11
12
2273
3
2829
2
2273
3
2830
4
2272
9
2830
4
197
374
604
149
6
241
5
5984
9660
7
8
9
10
11
12
2242
9
2777
6
2242
9
2778
8
2242
9
2778
8
198
379
615
151
6
245
9
6063
9836
7
8
9
10
11
12
2213
3
2728
0
2213
3
2729
1
2213
7
2729
1
199
384
627
153
7
250
7
6149
1002
8
7
8
9
10
11
12
2184
5
2675
7
2183
1
2676
8
2182
7
2676
8
200
389
639
155
9
255
5
6234
1022
0
7
8
9
10
11
12
2156
4
2625
5
2152
3
2626
5
2152
9
2626
5
201
395
651
158
0
260
3
6319
1041
2
7
8
9
10
11
12
2123
6
2577
1
2123
6
2578
1
2124
0
2578
1
202
400
663
160
1
265
1
6404
1060
4
7
8
9
10
11
12
2097
1
2530
5
2095
8
2531
4
2095
8
2531
4
HEVC
12
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Qinde
x
IQ_Scale
FQ_Shift
FQ_Quant
8b
10b
12b
8b
10b
12b
8b
10b
12b
DC
AC
DC
AC
DC
AC
D
C
A
C
D
C
A
C
D
C
A
C
DC
AC
DC
AC
DC
AC
203
406
676
162
4
270
3
6495
1081
2
7
8
9
10
11
12
2066
1
2481
8
2066
1
2482
7
2066
4
2482
7
204
411
689
164
7
275
5
6587
1102
0
7
8
9
10
11
12
2041
0
2435
0
2037
3
2435
8
2037
6
2435
8
205
417
702
167
0
280
7
6678
1122
8
7
8
9
10
11
12
2011
6
2389
9
2009
2
2390
7
2009
8
2390
7
206
423
715
169
2
285
9
6769
1143
7
7
8
9
10
11
12
1983
1
2346
4
1983
1
2347
2
1982
8
2347
0
207
429
729
171
7
291
5
6867
1166
1
7
8
9
10
11
12
1955
3
2301
4
1954
2
2302
1
1954
5
2301
9
208
435
743
174
1
297
1
6966
1188
5
7
8
9
10
11
12
1928
4
2258
0
1927
3
2258
7
1926
7
2258
6
209
441
757
176
6
302
7
7064
1210
9
7
8
9
10
11
12
1902
1
2216
2
1900
0
2217
0
1900
0
2216
8
210
447
771
179
1
308
3
7163
1233
3
7
8
9
10
11
12
1876
6
2176
0
1873
5
2176
7
1873
7
2176
5
211
454
786
181
7
314
3
7269
1257
3
7
8
9
10
11
12
1847
7
2134
5
1846
6
2135
1
1846
4
2135
0
212
461
801
184
4
320
3
7376
1281
3
7
8
9
10
11
12
1819
6
2094
5
1819
6
2095
1
1819
6
2095
0
213
467
816
187
1
326
3
7483
1305
3
7
8
9
10
11
12
1796
2
2056
0
1793
3
2056
6
1793
6
2056
5
214
475
832
190
0
332
7
7599
1330
9
7
8
9
10
11
12
1766
0
2016
4
1766
0
2017
0
1766
2
2016
9
215
482
848
192
9
339
1
7715
1356
5
7
8
9
10
11
12
1740
3
1978
4
1739
4
1979
0
1739
6
1978
8
216
489
864
195
8
345
5
7832
1382
1
7
8
9
10
11
12
1715
4
1941
8
1713
7
1942
3
1713
7
1942
2
217
497
881
199
0
352
3
7958
1409
3
7
8
9
10
11
12
1687
8
1904
3
1686
1
1904
8
1686
5
1904
7
218
505
898
202
1
359
1
8085
1436
5
7
8
9
10
11
12
1661
1
1868
2
1660
2
1868
8
1660
0
1868
6
219
513
915
205
4
365
9
8214
1463
7
8
8
10
10
12
12
3270
4
1833
5
3267
2
1834
0
3268
0
1833
9
220
522
933
208
8
373
1
8352
1492
5
8
8
10
10
12
12
3214
0
1798
2
3214
0
1798
6
3214
0
1798
5
221
530
951
212
380
8492
1521
8
8
10
10
12
12
3165
1764
3161
1764
3161
1764
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
13
Qinde
x
IQ_Scale
FQ_Shift
FQ_Quant
8b
10b
12b
8b
10b
12b
8b
10b
12b
DC
AC
DC
AC
DC
AC
D
C
A
C
D
C
A
C
D
C
A
C
DC
AC
DC
AC
DC
AC
3
3
3
5
1
0
6
0
5
222
539
969
215
9
387
6
8635
1550
2
8
8
10
10
12
12
3112
6
1731
3
3108
3
1731
3
3108
6
1731
6
223
549
988
219
7
395
2
8788
1580
6
8
8
10
10
12
12
3055
9
1698
0
3054
5
1698
0
3054
5
1698
3
224
559
100
7
223
6
402
8
8945
1611
0
8
8
10
10
12
12
3001
2
1666
0
3001
2
1666
0
3000
9
1666
2
225
569
102
6
227
6
410
4
9104
1641
4
8
9
10
11
12
13
2948
5
3270
4
2948
5
3270
4
2948
5
3270
8
226
579
104
6
231
9
418
4
9275
1673
4
8
9
10
11
12
13
2897
6
3207
8
2893
8
3207
8
2894
1
3208
2
227
590
106
6
236
3
426
4
9450
1705
4
8
9
10
11
12
13
2843
5
3147
6
2839
9
3147
6
2840
5
3148
0
228
602
108
7
241
0
434
8
9639
1739
0
8
9
10
11
12
13
2786
9
3086
8
2784
6
3086
8
2784
8
3087
2
229
614
110
8
245
8
443
2
9832
1772
6
8
9
10
11
12
13
2732
4
3028
3
2730
2
3028
3
2730
2
3028
7
230
626
112
9
250
8
451
6
1003
1
1806
2
8
9
10
11
12
13
2680
0
2972
0
2675
7
2972
0
2676
0
2972
3
231
640
115
1
256
1
460
4
1024
5
1841
4
8
9
10
11
12
13
2621
4
2915
2
2620
4
2915
2
2620
1
2915
5
232
654
117
3
261
6
469
2
1046
5
1876
6
8
9
10
11
12
13
2565
3
2860
5
2565
3
2860
5
2565
0
2860
8
233
668
119
6
267
5
478
4
1070
2
1913
4
8
9
10
11
12
13
2511
5
2805
5
2508
7
2805
5
2508
2
2805
8
234
684
121
9
273
7
487
6
1094
6
1950
2
8
9
10
11
12
13
2452
8
2752
6
2451
9
2752
6
2452
3
2752
9
235
700
124
3
280
2
497
2
1121
0
1988
6
8
9
10
11
12
13
2396
7
2699
4
2395
0
2699
4
2394
6
2699
7
236
717
126
7
287
1
506
8
1148
2
2027
0
8
9
10
11
12
13
2339
9
2648
3
2337
4
2648
3
2337
8
2648
5
237
736
129
2
294
4
516
8
1177
6
2067
0
8
9
10
11
12
13
2279
5
2597
0
2279
5
2597
0
2279
5
2597
3
238
755
131
7
302
0
526
8
1208
1
2107
0
8
9
10
11
12
13
2222
1
2547
7
2222
1
2547
7
2221
9
2548
0
239
775
134
3
310
2
537
2
1240
9
2148
6
8
9
10
11
12
13
2164
8
2498
4
2163
4
2498
4
2163
2
2498
7
HEVC
14
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Qinde
x
IQ_Scale
FQ_Shift
FQ_Quant
8b
10b
12b
8b
10b
12b
8b
10b
12b
DC
AC
DC
AC
DC
AC
D
C
A
C
D
C
A
C
D
C
A
C
DC
AC
DC
AC
DC
AC
240
796
136
9
318
8
547
6
1275
0
2190
2
8
9
10
11
12
13
2107
6
2451
0
2105
0
2451
0
2105
3
2451
2
241
819
139
6
328
0
558
4
1311
8
2233
4
8
9
10
11
12
13
2048
5
2403
6
2046
0
2403
6
2046
3
2403
8
242
843
142
3
337
5
569
2
1350
1
2276
6
8
9
10
11
12
13
1990
1
2358
0
1988
4
2358
0
1988
2
2358
2
243
869
145
1
347
8
580
4
1391
3
2321
4
8
9
10
11
12
13
1930
6
2312
5
1929
5
2312
5
1929
3
2312
7
244
896
147
9
358
6
591
6
1434
3
2366
2
8
9
10
11
12
13
1872
4
2268
7
1871
4
2268
7
1871
5
2268
9
245
925
150
8
370
2
603
2
1480
7
2412
6
8
9
10
11
12
13
1813
7
2225
0
1812
7
2225
0
1812
8
2225
2
246
955
153
7
382
3
614
8
1529
0
2459
0
8
9
10
11
12
13
1756
7
2183
1
1755
3
2183
1
1755
6
2183
2
247
988
156
7
395
3
626
8
1581
2
2507
0
8
9
10
11
12
13
1698
0
2141
3
1697
6
2141
3
1697
6
2141
4
248
102
2
159
7
408
9
638
8
1635
6
2555
1
8
9
10
11
12
13
1641
6
2101
0
1641
2
2101
0
1641
2
2101
1
249
105
8
162
8
423
6
651
2
1694
3
2604
7
9
9
11
11
13
13
3171
4
2061
0
3168
5
2061
0
3168
6
2061
1
250
109
8
166
0
439
4
664
0
1757
5
2655
9
9
9
11
11
13
13
3055
9
2021
3
3054
5
2021
3
3054
7
2021
4
251
113
9
169
2
455
9
676
8
1823
7
2707
1
9
9
11
11
13
13
2945
9
1983
1
2944
0
1983
1
2943
8
1983
1
252
118
4
172
5
473
7
690
0
1894
9
2759
9
9
9
11
11
13
13
2833
9
1945
1
2833
3
1945
1
2833
2
1945
2
253
123
2
175
9
492
9
703
6
1971
8
2814
3
9
9
11
11
13
13
2723
5
1907
5
2723
0
1907
5
2722
7
1907
6
254
128
2
179
3
513
0
717
2
2052
1
2868
7
9
9
11
11
13
13
2617
3
1871
4
2616
3
1871
4
2616
2
1871
4
255
133
6
182
8
534
7
731
2
2138
7
2924
7
9
9
11
11
13
13
2511
5
1835
5
2510
1
1835
5
2510
2
1835
6
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
15
SB, CU/PU and TU Sizes Encoder Only
CU/PU/TU Partitioning Configurations
SB size
CU size
min/max TU range
64x64
64x64
32x32..4x4
32x32
32x32..4x4
16x16
16x16..4x4
8x8
8x8..4x4
PU Options for a Given CU
Current CU size
Possible CU sizes
Allowed CU/PU partition types.
64x64
64x64
2Nx2N, 2NxN, Nx2N
32x32
2Nx2N, 2NxN, Nx2N
16x16
2Nx2N, 2NxN, Nx2N
8x8
2Nx2N, 2NxN, Nx2N, NxN
HEVC
16
Doc Ref # IHD-OS-KBL-Vol 10-1.17
Definition of the VP9 CU Record Structure - Encoder Only
The following table defines the CU record structure as indirect data to the PAK Object Command. Entries
are DW based (4 bytes) and cache aligned. This memory surface is pointed to by the HCP Indirect CU
Object Base Address in the HCP_IND_OBJ_BASE_ADDR_STATE Command.
VP9 CU Record Structure Definition (UnPacked CU)
DW
Bit
Field
Bits
Definition
Comments
0
1:0
cu_size
2
0: 8x8,
1:16x16,
2: 32x32, and
3: 64x64
Indicates size of the CU
3:2
Reserved
4
MBZ
5:4
cu_part_mode
2
0: 2Nx2N,
1: 2NxN,
2: Nx2N,
3: NxN (8x8 only)
7:6
Reserved
2
MBZ
11:8
intra_chroma_mode[0][3:0]
4
0:DC_PRED
1:V_PRED
2:H_PRED
3:TM_PRED
4:D45_PRED
5:D135_PRED 6:D117_PRED
7:D153_PRED 8:D207_PRED
9:D63_PRED
10-15 Reserved
15:12
Reserved
4
MBZ
19:16
intra_chroma_mode[1][3:0]
4
0:DC_PRED
1:V_PRED
2:H_PRED
3:TM_PRED
4:D45_PRED
Applicable for part1 of shapes >
8x8
HEVC
Doc Ref # IHD-OS-KBL-Vol 10-1.17
17
DW
Bit
Field
Bits
Definition
Comments
5:D135_PRED 6:D117_PRED
7:D153_PRED 8:D207_PRED
9:D63_PRED
10-15 Reserved
20
cu_pred_mode0
1
0: Intra
1: Inter
Pred mode for part0 in raster
scan order
cu_pred_mode=intra means
ref_refframe0=intra
21
cu_pred_mode1
1
0: Intra
1: Inter
Pred mode for part1 in raster
scan order
cu_pred_mode=intra means
ref_refframe0=intra
23:22
Reserved
2
MBZ
24
interpred_comp0
1
0: Single
1:
Compound(ref_refframe1>intra)
Interpred comp mode for Part0
25
interpred_comp1
0
0: Single
1:
Compound(ref_refframe1>intra)
Interpred comp mode for Part1
31:26
Reserved
6
MBZ
1
3:0
intra_mode[0][3:0]
4
0:DC_PRED
1:V_PRED
2:H_PRED
3:TM_PRED
4:D45_PRED
5:D135_PRED 6:D117_PRED
7:D153_PRED 8:D207_PRED
9:D63_PRED
Luma Intra mode for part0
7:4
Reserved
4
11:8
intra_mode[1][3:0]
4
Luma pred mode for part1
15:12
Reserved
4
19:16
intra_mode[2][3:0]
4
Luma pred mode for part2;
HEVC
18
Doc Ref # IHD-OS-KBL-Vol 10-1.17
DW
Bit
Field
Bits
Definition
Comments
applicable for 4x4 only
23:19
Reserved
4
27:24
intra_mode[3][3:0]
4
Luma pred mode for part3;
applicable for 4x4 only
31:28
Reserved
4
2
15:0
mvx_refframe0[0][15:0]
16
Frame0(Forward) MVx for part0
16-bit each(2's complement with
3 fractional bits); encodable
range is [-16382,16382]).
31:16
mvy_refframe0[0][15:0]
16
Frame0(Forward) MVy for part0
16-bit each(2's complement with
3 fractional bits); encodable
range is [-16382,16382]).
3
15:0
mvx_refframe0[1][15:0]
16
Frame0 (Forward) MVx for part1
16-bit each(2's complement with
3 fractional bits); encodable
range is [-16382,16382]).
31:16
mvy_refframe0[1][15:0]
16
Frame0 (Forward) MVy for part1
16-bit each(2's complement with
3 fractional bits); encodable
range is [-16382,16382]).
4
15:0
mvx_refframe0[2][15:0]
16
31:16
mvy_refframe0[2][15:0]
16
5
15:0
mvx_refframe0[3][15:0]
16
31:16
mvy_refframe0[3][15:0]
16
6
15:0
mvx_refframe1[0][15:0]
16
31:16
mvy_refframe1[0][15:0]
16
7
15:0
mvx_refframe1[1][15:0]
16
31:16
mvy_refframe1[1][15:0]
16
8
15:0
mvx_refframe1[2][15:0]
16
Interleaved X and Y
31:16
mvy_refframe1[2][15:0]
16
9
15:0
mvx_refframe1[3][15:0]
16
31:16
mvy_refframe1[3][15:0]
16
10
1:0
ref_refframe0[0][1:0]
2
0:intra
frame0(forward)reference frame
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DW
Bit
Field
Bits
Definition
Comments
1:last
2:golden
3:altref
id for part0
HW uses if
SegmentReferenceEnabled=0 in
segment ID command
3:2
Reserved
2
MBZ
5:4
ref_refframe0[1][1:0]
2
0:intra
1:last
2:golden
3:altref
frame0(forward)reference frame
id for part1
7:6
Reserved
2
MBZ
9:8
ref_refframe1 [0][1:0]
2
0:intra
1:last
2:golden
3:altref
frame1(backward)reference
frame id for part0
11:10
Reserved
2
MBZ
13:12
ref_refframe1 [1][1:0]
2
0:intra
1:last
2:golden
3:altref
frame0(forward)reference frame
id for part1
15:14
Reserved
2
MBZ
18:16
QuantRound0
3
0:+1/16
1:+2/16
2:+3/16
3:+4/16
4:+5/16
5:+6/16(default)
6:+7/16
7:+8/16
Quantization Round value for
Part0 (8x8 and below shapes will
have the same round value)
19
Reserved
MBZ
22:20
QuantRound1
3
0:+1/16
Quantization Round value for
Part1
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DW
Bit
Field
Bits
Definition
Comments
1:+2/16
2:+3/16
3:+4/16
4:+5/16
5:+6/16(default)
6:+7/16
7:+8/16
31:23
Reserved
1
MBZ
11
1:0
tu_size[0][1:0]
2
0: 4x4
1: 8x8
2: 16x16
3: 32x32
tu_size[2][1:0], tu_size[3][1:0]
must be 0 (4x4)
11
3:2
tu_size[1][1:0]
2
0: 4x4
1: 8x8
2: 16x16
3: 32x32
11
13:4
Reserved
10
MBZ
11
14
segmentPredFlag0
1
0:Diaable
1:Enable
Segment Prediction disable for
Part0
11
15
segmentPredFlag1
1
0:Diaable
1:Enable
Segment Prediction disable for
Part1
11
18:16
SegmentIdx[0][2:0]
3
Segment 0 to 7
SegmentID for part0 of blocks >
8x8
11
21:19
SegmentIdx[1][2:0]
3
Segment 0 to 7
SegmentID for part1 of blocks >
8x8
11
23:22
MotionComp_flttype[0][1:0]
2
0: EIGHTTAP
1: EIGHTTAP_SMOOTH
2: EIGHTTAP_SHARP
3: BILINEAR
HW will use this filtertype if
SWITCHABLE=1 in pic state;
Used for part0
11
25:24
MotionComp_flttype[1][1:0]
2
0: EIGHTTAP
For part1 of blocks >8x8
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DW
Bit
Field
Bits
Definition
Comments
1: EIGHTTAP_SMOOTH
2: EIGHTTAP_SHARP
3: BILINEAR
11
31:26
Reserved
6
MBZ
12..15
31:0
Reserved
MBZ
Allowed SB Size Encoder Only
The following table details the SB size allowed and the number of records per SB for the encoder.
Allowed SB Size Encoder Only
SB Size Allowed
Number of Records per SB
64x64
64
Note: HW will support partial SBs within a frame bourndary to a minimun CU8x8 granularity
HCP Commands
The HCP Commands specify the HEVC BSD object and PAK object level configuration.
HCP_BSD_OBJECT (VideoCS)
HCP_PAK_OBJECT_VideoCS
HCP_PAK_INSERT_OBJECT_VideoCS
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Multipass flow during BRC and SAO
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CU and Slice level stat streamOut
Along with final bitstream, HLC writes out two statistics related streamout cachelines to the memory.
Streamout0 cacheline is composed of 4 quarter cachelines, each containing information on CU skip flag,
coding block flag for the TUs in a CU, residual/coefficient bit count for a CU, total bit count for CU, LCU
exceed limit flag. A typical streamout0 cacheline, therefore, has information on statistics for 4 CUs and
lcu exceed limit flag.
Streamout1 cacheline is composed of quarter cachelines., each quarter cacheline consisting of bit count
of current slice.
Pak pipeline streamout enable bit, set by HCP_PIPE_MODE_SELECT command, enables or disables the
streamout.
Streamout 0: Per CU Quarter Cacheline Format
Level
Field
Width
Cacheline
Comment
CU
CU Skip Flag
1
qcacheline[0]
Packed in Quarter Cacheline in CU format
LCU
LCU exceed limit
1
qcacheline[1]
Packed in Quarter Cacheline in CU format (valid
in last CU of LCU)
Reserved
14
qcacheline[15:2
Reserved
CU
TU CBF Y/U/V
48
qcacheline[63:16]
Packed in Quarter Cacheline in CU format
CU
CU Coefficient Bit Count (Only
residual)
18
qcacheline[81:64]
Packed in Quarter Cacheline in CU format
CU
CU Bit Count (all CU Syntax)
18
qcacheline[113:96]
Packed in Quarter Cacheline in CU format
Reserved
14
qcacheline[127:114]
Reserved
Streamout 1: Per Slice Quarter Cacheline
Level
Field
Width
Cacheline
Comment
Slice
Slice Bit Count (slice header + data + tail)
32
cacheline[31:0]
Reserved
32
cacheline[63:32]
SlicePositionX[15:0]
16
cacheline[79:64]
SlicePositionY[15:0]
16
cacheline[95:80]
Reserved
32
cacheline[127:96]
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Definition of the CU Record Structure for Ext Interface Encoder Only
The following table defines the CU record structure as indirect data to the PAK Object Command. Entries
are DW based (4 bytes) and cache aligned. This memory surface is pointed to by the HCP Indirect CU
Object Base Address in the HCP_IND_OBJ_BASE_ADDR_STATE Command.
CU Record Structure Definition
DWord
Bitfield
Field
Bits
Definition
Comments
0
1:0
cu_size
2
0: 8x8
1: 16x16
2: 32x32
3: 64x64
2
cu_pred_mode
1
0: Intra
For I slices, pred_mode is always 0.
1: Inter
3
cu_transquant_bypass_flag
1
Note: HW ignores this bit for RhoDomain
calculation so the statics will be slightly
inaccurate.
This bit should not be set to 1 if
transform_skip=1
6:4
cu_part_mode
3
0: 2Nx2N
1: 2NxN (inter
only)
2: Nx2N (inter
only)
3: NxN (intra
only)
only if CU size is 8x8
4: 2NxhN (inter
only)
5: hNx2N (inter
only)
7
IPCM_enable
1
1: Enable IPCM
0: Disable IPCM
MBZ Reserved
If IPCM is enabled, then entire CU is IPCM
predicted. Both PU and TU sizes should be
same as CU size. Cu_pred_mode is ignored
when IPCM is enbled.
Note: Supports 8bit pixel depth only
10:8
intra_chroma_mode
3
0: DM
(use Luma mode, from block 0 if NxN)
1: Reserved
(supposedly to be defined for LM mode)
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DWord
Bitfield
Field
Bits
Definition
Comments
2: Planar
3: Vertical
4: Horizontal
5: DC
11
zero_out_coefficient
1
0: Do not force
coefficients to
zero
1: Force
coefficients to
zero
If this bit it set to 1, HW will force coefficients
to zero.
15:12
Reserved
5
22:16
cu_qp
7
in 7-bit
Valid range: 0 to 51 for 8bit mode
-12 to 51 for 10bit mode
diff_cu_qp_delta_depth = 0 (No QP change
allowed at CU Level.
Only allow QP change across LCU, no
change across CU for PAK only.
23
cu_qp_sign
1
0:positive
1:negative
Indicates sign bit for QP.
Must be zero for 8bit mode
31:24
interpred_idc[3:0][1:0]
8
2 bits each 0: L0
1: L1 2: Bi 3:
reserved
in Z-order interpred_idc[0][1:0] - block 0 =
[25:24] interpred_idc[15][1:0] - block 15 =
[31:30]
1
5:0
intra_mode[0][5:0]
6
final explicit
luma mode.
Valid values are
0..34.
1 per cu partition, and only active partitions
have valid intra mode value
7:6
Reserved
2
13:8
intra_mode[1][5:0]
6
final explicit
luma mode.
Valid values are
0..34.
15:14
Reserved
2
21:16
intra_mode[2][5:0]
6
final explicit
luma mode.
Valid values are
0..34.
23:22
Reserved
2
29:24
intra_mode[3][5:0]
6
final explicit
luma mode.
Valid values are
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DWord
Bitfield
Field
Bits
Definition
Comments
0..34.
31:30
Reserved
2
2
15:0
31:16
mvx_l0[0][15:0]
mvx_l0[1][15:0]
64
16-bit each
[0] in the least sig position
in Z-order (1st index starts at LSB and goes
up)
3
15:0
31:16
mvx_l0[2][15:0]
mvx_l0[3][15:0]
4
15:0
31:16
mvy_l0[0][15:0]
mvy_l0[1][15:0]
64
16-bit each
in Z-order (1st index starts at LSB and goes
up)
5
15:0
31:16
mvy_l0[2][15:0]
mvy_l0[3][15:0]
6
15:0
31:16
mvx_l1[0][15:0]
mvx_l1[1][15:0]
64
16-bit each
in Z-order (1st index starts at LSB and goes
up)
7
15:0
31:16
mvx_l1[2][15:0]
mvx_l1[3][15:0]
8
15:0
31:16
mvy_l1[0][15:0]
mvy_l1[1][15:0]
64
16-bit each
in Z-order (1st index starts at LSB and goes
up)
9
15:0
31:16
mvy_l1[2][15:0]
mvy_l1[3][15:0]
10
3:0 7:4
11:8
15:12
reserved[0]
intra_chroma_mode1[2:0]
reserved[0]
intra_chroma_mode2[2:0]
reserved[0]
intra_chroma_mode3[2:0]
reserved[3:0]
3-bits each
10
3:0 7:4
11:8
15:12
ref_idx_l0[0][3:0]
ref_idx_l0[1][3:0]
ref_idx_l0[2][3:0]
ref_idx_l0[3][3:0]
16
4-bit each
in Z-order (1st index starts at LSB and goes
up)
19:16
23:20
27:24
31:28
ref_idx_l1[0][3:0]
ref_idx_l1[1][3:0]
ref_idx_l1[2][3:0]
ref_idx_l1[3][3:0]
16
4-bit each
Combined list is not supported
in Z-order (1st index starts at LSB and goes
up)
11
tu_size[15:0]
32
0: 4x4
in Z-order (1st index starts at LSB and goes
up)
1: 8x8
2: 16x16
3: 32x32
12
15:0
tu_xform_Yskip[15:0]
16
0: TU transform
skip flag for
luma
In Z-order (1st index starts at LSB and goes
up).
Populated for each TU even if transform skip
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DWord
Bitfield
Field
Bits
Definition
Comments
component is
not set (normal
transform)
1: TU transform
skip flag for
luma
component is
set
is not supported for that particular TU size.
This bit should not be set to 1 if
transquant_bypass=1
27:16
Reserved
12
31:28
tu_countm1[3:0]
4
number of TU
count per CU
minus 1
Intel restriction max 16 TU per CU (however
spec allows up to 256 TUs).
If there is no TU inside a CU, it is indicated
by cbf and skip flag.
13
15:0
tu_xform_Uskip[15:0]
16
0: TU transform
skip flag for
chroma cb
component is
not set (normal
transform)
1: TU transform
skip flag for
chroma cb
component is
set
Indexed by tu_xform_Yskip index. Populated
for each TU even if transform skip is not
supported for that particular TU size.
For the case where a 4x4 chroma TU is
associated with a group of four 4x4 luma TUs
the chroma cb transform skip is coded in the
same position as the last 4x4 luma TU (the
prior 3 indexed positions are
skipped/ignored). For example an 8x8 CU
with four 4x4 luma TUs would code the
chroma cb TU transform skip flag as
tu_xform_Uskip[3].
Restriction: For 422, 2 TUs for each Chroma
correspond to 1 Luma TU share the same
transformskip flag.
This bit should not be set to 1 if
transquant_bypass=1
31:16
tu_xform_Vskip[15:0]
16
0: TU transform
skip flag for
chroma cr
component is
not set (normal
transform)
1: TU transform
skip flag for
chroma cr
component is
set
Indexing identical tu_xform_Uskip.
Populated for each TU even if transform skip
is not supported for that particular TU size.
This bit should not be set to 1 if
transquant_bypass=1
Intel restriction max 16 TU per CU, max 256 TUs in a CU.
Max 64 CUs, and each CU record max is 1 cacheline 64 bytes in size (1 cacheline 64 bytes)
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LCU, CU, TU, and PU Sizes Encoder Only
LCU/CU Partitioning Configurations
LCU size
min CU size
CU Depth
Hierarchical Depth=CU Depth+1
64x64
64x64
0
1
32x32
1
2
16x16
2
3
8x8
3
4
32x32
32x32
0
1
16x16
1
2
8x8
2
3
16x16
16x16
0
1
8x8
1
2
8x8
8x8
X
Not allowed in spec
PU Options for a Given CU
Current CU size (leaf node)
min CU sizes (Pic State)
Allowed
PU
partition
types.
64x64 (2Nx2N)
Must be a LCU
64x64
Skip :
2Nx2N
Intra :
2Nx2N,
NxN
Inter :
2Nx2N,
2NxN,
Nx2N, NxN
32x32
Skip :
2Nx2N
Intra :
2Nx2N (no
NxN
defined in
the spec.)
Inter :
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2Nx2N,
2NxN,
Nx2N,
2NxnU,
2NxnD,
nLx2N,
nRx2N
16x16
Skip :
2Nx2N
Intra :
2Nx2N (no
NxN
defined in
the spec.)
Inter :
2Nx2N,
2NxN,
Nx2N,
2NxnU,
2NxnD,
nLx2N,
nRx2N
8x8
Skip :
2Nx2N
Intra :
2Nx2N (no
NxN
defined in
the spec.)
Inter :
2Nx2N,
2NxN,
Nx2N,
2NxnU,
2NxnD,
nLx2N,
nRx2N
32x32 (2Nx2N)
Can or is not a LCU
32x32
Skip :
2Nx2N
Intra :
2Nx2N,
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NxN
Inter :
2Nx2N,
2NxN,
Nx2N, NxN
16x16
Skip :
2Nx2N
Intra :
2Nx2N
Inter :
2Nx2N,
2NxN,
Nx2N,
2NxnU,
2NxnD,
nLx2N,
nRx2N
8x8
Skip :
2Nx2N
Intra :
2Nx2N
Inter :
2Nx2N,
2NxN,
Nx2N,
2NxnU,
2NxnD,
nLx2N,
nRx2N
16x16 (2Nx2N)
Can or is not a LCU
16x16
Skip :
2Nx2N
Intra :
2Nx2N,
NxN
Inter :
2Nx2N,
2NxN,
Nx2N, NxN
8x8
Skip :
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2Nx2N
Intra :
2Nx2N
Inter :
2Nx2N,
2NxN,
Nx2N,
2NxnU,
2NxnD,
nLx2N,
nRx2N
8x8 (2Nx2N)
Cannot be a LCU
8x8
Skip :
2Nx2N
Intra :
2Nx2N and
NxN
Inter :
2Nx2N,
2NxN,
Nx2N (both
NxN and
AMP are
not allowed
for 8x8
inter CU)
Note: In an 8x8 Inter CU NxN isn’t allowed if the SPS parameter disable_inter_4x4 is 1. In Main profile
currently this flag is always 1.
U.D, L and R (Up, Down, Left and Right)
n = ¼ or .
TU Partitioning for a Given CU
CU
size
TU
size
TU
Depth
Max Depth=TU
Depth+1
PAK supported TU sizes and corresponding number of
TUs in CU
64x64
64x64
0
1
no 64x64 transform, so automatically breakdown into 4
32x32 TUs.
32x32
1
2
number of TUs in CU = 4
16x16
2
3
number of TUs in CU = 16
8x8
3
4
this configuration is currently not supported.
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4x4
4
5
this configuration is currently not supported.
32x32
32x32
0
1
number of TUs in CU = 1
16x16
1
2
number of TUs in CU = 4
8x8
2
3
number of TUs in CU = 16
4x4
3
4
this configuration is currently not supported.
16x16
16x16
0
1
number of TUs in CU = 1
8x8
1
2
number of TUs in CU = 4
4x4
2
3
number of TUs in CU = 16
8x8
8x8
0
1
number of TUs in CU = 1
4x4
1
2
number of TUs in CU = 4
The actual level of partitioning is governed by
MaxTUSize and MinTUSize in Pic State.
max_transform_hierarchy_depth_inter <= 2 (intel restriction) DW4 bit 3:2 Pic State
max_transform_hierarchy_depth_intra <= 2 (intel restriction) DW4 bit 1:0 Pic State
Allowed LCU Size Encoder Only
The following table details the LCU size allowed and the number of records per LCU for the encoder.
LCU Size Allowed
Fixed Number of Records per LCU
64x64
64
32x32
16
16x16
4
Note: 0.5 CL per CU record in VME mode and 1 CL per CU record in extENC mode.
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HEVC Error Concealment
The HCP implements an error concealment policy, which is always enabled and cannot be disabled. The
objective is that the HCP will always complete a frame/field workload by either decoding the bit stream
normally until it finishes the workload or by concealing blocks until the slice or workload is completed. It
should never be allowed to hang.
Error concealment, implemented by the HCP hardware, is configured for each slice in the
HCP_BSD_OBJECT command. The following information in the HCP_BSD_OBJECT command is utilized for
error concealment.
SliceStartCtbY, SliceStartCtbX: The current slice position specified in Ctb coordinates.
NextSliceStartCtbY, NextSliceStartCtbX: The next slice position specified in Ctb coordinates. If
the current slice is the last slice in the picture, the next slice values are set to (0,0).
LastSliceofPic: Indicates that the current slice is the last slice in the picture.
slice_type: Indicates the picture type: I, P or B.
The host software will remove all extra slices in the picture. The HCP will not be given a workload that
includes extra slices beyond the picture. The last slice in the picture will always be marked by the host
software.
The host software will remove any overlapping slices in the picture. The HCP will not be given a workload
that includes overlapping slices in the picture.
A HCP_BSD_OBJECT command will include the current slice position and the next slice position. For non-
errored streams, it is guaranteed that the slice bit stream will be decoded by the HCP starting from the
current slice position through to the Ctb (inclusive) adjacent to the Ctb indicated by the next slice
position. HEVC Error Concealment illustrates the example of a non-errored stream decode starting with
XXX.
HEVC Slice Decode for Non-errored Stream Cases
For error stream cases where the next slice position does not align itself with the last successfully
decoded Ctb in the current slice, the HCP will conceal Ctbs from the last decoded Ctb in the current slice
through to the last Ctb prior to the Ctb indicated by the next slice position. If the error occurs such that
the current decoded Ctb cannot be decoded, the HCP will ensure that the current Ctb is written out by
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any means before writing out concealed Ctbs for the remaining Ctbs in the current slice. In the case of
the last slice in a picture, the HCP will conceal Ctbs from the last decoded Ctb in the current slice through
to the last Ctb position in the picture indicated by the resolution of the picture in the HCP_PICT_STATE
command. HEVC Error Concealment illustrates the case described.
HEVC Slice Decode for Missing Blocks in a Slice
Since the host software removes overlapping slices, the next slice position will never be equal to or less
than the current slice position.
A concealed Ctb for an I-slice is constructed by the HCP specifying the Intra_Planar prediction mode for
the Ctb.
A concealed Ctb for a P-slice is constructed by the HCP specifying the skip_flag.
A concealed Ctb for a B-slice is constructed by the HCP specifying the skip_flag.
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VP9 Register Definitions
This section describes the VP9 Register Definitions as follows:
Register Attributes Description
VP9 Register Map
VP9 Encoder Register Descriptions
Register Attributes Description
Host Register Attributes gives the defined register tags and their description.
Host Register Attributes
Tag
Name
Description
R/W
Read/Write
Bit is read and writeable.
R/SW
Read/Special Write
Bit is readable. Write is only allowed once after a reset.
RO
Read Only
Bit is only readable, but writes have no effects.
WO
Write Only
Bit is only writeable, reads return zeroes.
RV
Reserved
Bit is reserved and not visible. Reads will return 0, and writes have no effect.
NA
Not Accessible
This bit is not accessible.
VP9 Register Map
These are MMIO register definitions for decoder/encoder:
VP9 Encoder Register Descriptions
HCP_IMAGE_STATUS_MASK - HCP Image Status Mask
HCP_IMAGE_STATUS_CONTROL - HCP Image Status Control
HCP_UNIT_DONE - HCP Unit Done
HEVC Register Definitions
The Message Channel Interface is a read-only bus used to access the HCP status registers. All registers
are 32 bits where reserved bits return a value of zero and subtractive-decode is used to return 0x0000 for
all register holes. The Unit ID is 28h. For HCP, the address range is 0x0001E900h to 0001E9FFh.
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Register Attributes Description
Host Register Attributes gives the defined register tags and their description.
Host Register Attributes
Tag
Name
Description
R/W
Read/Write
Bit is read and writeable.
R/SW
Read/Special Write
Bit is readable. Write is only allowed once after a reset.
RO
Read Only
Bit is only readable, but writes have no effects.
WO
Write Only
Bit is only writeable, reads return zeros.
RV
Reserved
Bit is reserved and not visible. Reads will return 0, and writes have no effect.
NA
Not Accessible
This bit is not accessible.
HCP Decoder Register Map
This documents all HEVC Decoder MMIO Registers.
HCP Decoder Register Descriptions
The HCP implements the following MMIO registers. A description of the register including its address
and DWord descriptions are provided.
HCP CABAC Status
HCP Picture Checksum cIdx0
HCP Picture Checksum cIdx1
HCP Picture Checksum cIdx2
HCP Encoder Register Map
These are MMIO register definitions for encoder.
HCP Encoder Register Descriptions
HCP_FRAME_PERFORMANCE_CT - HCP Frame Performance Count
HCP_LAT_CT1 - HCP Memory Latency Count1
HCP_LAT_CT2 - HCP Memory Latency Count2
HCP_LAT_CT3 - HCP Memory Latency Count3
HCP_LAT_CT4 - HCP Memory Latency Count4
HCP_LAT_CT5 - HCP Memory Latency Count5
HCP_LAT_CT6 - HCP Memory Latency Count6
HCP_BIN_CT - HCP Frame BitStream BIN Count
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HCP_READ_CT - HCP Frame Motion Comp Read Count
HCP_MISS_CT - HCP Frame Motion Comp Miss Count
HCP_BITSTREAMSE_BITCOUNT_FRAME - Reported Bitstream Output Bit Count for Syntax Elements
Only
HCP_CABAC_BIN_COUNT_FRAME - Reported Bitstream Output CABAC Bin Count Register
HCP_CABAC_INSERTION_COUNT - Reported Bitstream Output CABAC Insertion Count
HCP_MINSIZE_PADDING_COUNT - Bitstream Output Minimal Size Padding Count Report Register
HCP_IMAGE_STATUS_CONTROL - HCP Image Status Control
HCP_QP_STATUS_COUNT - HCP Qp Status Count
HCP_UNIT_DONE - HCP Unit Done
HCP_IMAGE_STATUS_MASK - HCP Image Status Mask
HUC Status Register Descriptions
Following are HUC Status Register Descriptions:
UKERNEL_HDR_INFO - uKernel Header Info
Acronyms and Applicable Standards
Acronyms and Abbreviations
The table below defines acronyms and abbreviations used in this document.
Acronyms
Acronym
Meaning
AAC
Advanced Audio Coding part of the MPEG specification, AAC is the latest development in audio
compression. It provides higher-quality audio reproduction than MPEG-1 Layer 3 (MP3), while
requiring nearly 50% less data. It is defined in ISO/IEC 13818-7.
ADSL
Asymmetrical Digital Subscriber Line an asymmetrical DSL technology that takes advantage of
the one-way nature of most multimedia communication, and provides much faster data rates for
downstream (to the subscriber) then the upstream.
API
Application Programming Interface a set of routines used by an application program to request
and carry out low-level services performed by the operating system.
ARGB
Alpha Red Green Blue color channel components.
ARIB
Association of Radio Industries and Business designated by the Ministry of Public Management,
Home Affairs, Posts and Telecommunications (MPHPT) in Japan. ARIB members include
broadcasters, radio equipment manufacturers, telecommunication operators, and related
organizations.
ASP
Advanced Simple Profile MPEG4-2
ATSC
ATSC Advanced Television Systems Committee an organization in US that establishes and
promotes technical standards for advanced television systems, such as digital television (DTV).
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Acronym
Meaning
BDU
Bit-stream Data Unit
BIST
Built In Self Test
BPP
Bits Per Pixel
BSD
Byte Stream Decoder
CA, CAM
Conditional Access, Conditional Access Module the removable descrambling module
implemented in digital cable or satellite television system. The data flows through the module,
which can have any proprietary scrambling algorithm implemented, yet maintaining system
interface compatibility. The CAMs are usually provided by the operators in the TV network.
CPU
Central Processing Unit
DAA
Direct Access Arrangement
DAC
Digital-to-Analog Converter
DDA
Digital Difference Analyzer
DDS
Direct Digital Synthesizer
DPB
Decoded Picture Buffer. This buffer holds the decoded pictures for reference and for output along
with the currently decoding picture. This differs from the DPB in the standard, which only holds the
decoded pictures for reference.
DVB
Digital Video Broadcasting a set of open worldwide standards that define digital broadcasting
using existing satellite, cable, and terrestrial infrastructures. It uses MPEG-2 specification as a
universal foundation and expands it with DVB data structures and processes DVB-compliant digital
broadcasting and equipment is widely available to consumers and is indicated with the DVB logo.
DVB-S
Satellite television DVB standards, based on QPSK and 8-DPSK modulation.
DVB-T
Terrestrial television DVB standards, based on 2k and 8k OFDM modulation.
DVD
Digital Versatile Disc
DVD-R
Recordable DVD. Since different disk formats are currently in use, including DVD-R,DVD+R, they are
collectively mentioned as DVD-R in this document
DVI
Digital Visual Interface standard (EIA/CEA-861A). The standard defines a method for sending digital
video signals over DVI and OpenLDI interface specifications. The standard is fully backward
compatible with earlier DVI standards. New features include carrying auxiliary video information,
such as aspect ratio and native video format information.
DVO
Digital Video Output - the parallel, low voltage signaling interface defined for Intel® video chipsets
DSL
xDSL
Digital Subscriber Line transmission of data over copper telephone lines capable of bringing high-
bandwidth to subscribers. Many flavors of DSL are currently in use, which are collectively called
xDSL throughout the document.
DSP
Digital Signal Processor
DST
Destination
DWord
A 32-bit word
ES
Elementary Streams the raw output of an encoder, containing only what is necessary for a
decoder to approximate the original picture or audio.
FIFO
First in First Out
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Acronym
Meaning
FIR
Finite Impulse Response
FPU
Floating Point Unit
FW
Firmware running on the decoder controller, as used in Volume 4 of the Olo River Plus Silicon EAS
IDR
Instantaneous Decoding Refresh
IEEE 1394
1394
IEEE 1394 or iLink* or FireWire* An IEEE electronics industry standard for connecting multimedia
and computing Up to 63 devices can be attached to your PC via a single plug-and-socket
connection.
IEEE 802.11
802.11
The Institute for Electronics and Electrical Engineers (IEEE) wireless network specification. 802.11g
and 802.11a networks can transmit payload at the rates in excess 34Mbits/s and allow for the
wireless transmission at distances from several dozen to several hundred feet indoors.
IF
Intermediate Frequency the fixed, relatively low-frequency carrier to which current programs are
ported by the tuner.
GMCH
Graphics and Memory Control Hub a chip that connects the IA processor to memory and other
components in PC.
HDD
Hard Disk Drive magnetic mass storage device used in media centers for audiovisual program
recording.
HDMI
High Definition Multimedia Interface (HDMI). This interface is used between any audio/video
source, such as a set-top box, DVD player, or A/V receiver, and an audio or video monitor, such as a
DTV. HDMI supports standard, enhanced or high-definition video, plus multi-channel digital audio
on a single cable. The format transmits all ATSC HDTV standards and supports eight-channel digital
audio (at up to a 192kHz sampling rate), with bandwidth to spare for future enhancements.
HDTV
High-Definition Television HDTV specifically refers to the highest-resolution formats of the 18
total DTV formats, true HDTV is generally considered to be 1,080-line interlaced (1080i) or 720-line
progressive (720p).
HSR
Hidden Surface Removal
HW
Hardware
I/F
Interface
IEEE
IEEE 32-bit Floating Point number format representation
ISP
Image Synthesis Processor A collective term to describe all components of the hidden surface
removal operation within the PowerVR architecture.
LOD
Level Of Detail used in texturing calculations.
LSB
Least Significant Bit
LUT
Look-up table
MBAFF
Block Adaptive Field Frame mode
MFD
Multi-Format Decoder
MMU
Memory Management Unit
MMMC
Multi-port, Multi-channel Memory Controller
MSA
Intel Micro Signal Architecture microprocessor architecture combining the features of
microcontroller and digital signal processor. MSA is used here as a synonym of the processor core
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Acronym
Meaning
used in Olo River Plus
MSB
Most Significant Bit
MPEG
Motion Picture Experts Group Organization that develops standards for digital video and digital
audio compression.
MPR
Inter Prediction Module
NAL
Network Abstraction Layer
NAL unit
Syntax structure in a H.264 stream
NTSC
National Television System Committee, North American 525-line analog broadcast TV standard.
NIM
Network Interface Module the integrated tuner and digital demodulator in the (satellite) TV
systems. The DVB NIMs output MPEG transport stream.
NOP
No operation
OEM
Original Equipment Manufacturer
OGL/OpenGL
Open GL application programming interface
PAL
Phase Alternation Line - TV standard used in Europe. PAL uses 625 lines per frame, a 25 frames per
second update rate and YUV color encoding. The number of visible pixels for PAL video is 768 x
576.
PCI
Peripheral Component Interconnect bus, a bi-directional bus defined in PCI 2.x specification
PES
Packetized Elementary Streams packetized streams are the ES streams arranged in data packets
with PES header starting every packet. The syntax of the ES and PES is defined in MPEG. See
definition for ES.
PIP
Picture In Picture display mode
POD
Point of Deployment conditional access module the removable conditional access module
defined in the OpenCable* specification in US.
PPS
Picture Parameter set
PTS
Presentation time stamp
PVR
Personal Video Recorder, also PDR or personal digital recorder an interactive TV-recording
device that records programs in digital format and allows users to search for/record shows based
on type (for instance all basketball games or all episodes of a particular program). Users can also
pause, rewind, stop, or fast-forward live programs with only a small time lag.
PWL
Piece-wise Linear
PXD
Pixel Decoder Module
RF
Radio Frequency usually, modulated carriers which can be directly received by the tuners of TVs
or radio receivers
RISC
Reduced Instruction Set Computer
RHW
Reciprocal Homogenous W W is a 3-D coordinate representation like X Y Z
RSB
Row Store Buffer
RTL
Register Transfer Language/Level
SEI
Supplementary Enhancement Information
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Acronym
Meaning
SIF
Semaphore Interface Module
SIMD
Single Instruction Multiple Data
SMPTE
Society of Motion Picture and Television Engineers
SOC
System on chip
SP
Simple Profile MPEG4-2
SPS
Sequence Parameter set
SRC
Source
SDTV
Standard-Definition Television a digital television system that is similar to current analog TV
standards in picture resolution and aspect ratio. Typical SDTV resolution is 480i or 480p.
STB
Set Top Box a device that effectively turns a television set into an interactive Internet device
and/or allows the television to receive and decode digital television (DTV) broadcasts.
TA
Tile Accelerator
TS
MPEG-2 Transport Stream a sequence of 188-byte packets carrying the multi-program
audiovisual data
TSP
Texture Shading Processor a collective term to describe all components of the texture, shading
and pixel blending operations within the PowerVR architecture.
VCL
Video Coded Layer
VCXO
Voltage Controlled Crystal Oscillator
VGP/ VGP Lite
Vertex Geometry Processor
VLC
Variable length coded. This refers to the collection of coding techniques that are used in VC1, and
include CABAC, CAVLC and Exp-Golomb.
VOL
Video Object Layer
VOP
Video Object Plane
WAN
Wide Area Network
WSS
Wide Screen Signaling
XDS
Extended Data Services data services sending data in line 21/283 of the analog NTSC TV signal
XSI
Intel® XScale® System Interconnect
X, Y, Z, W
3-D coordinate representations
YUV
YUV texture format, primarily for video formats